参数资料
型号: HFA3860AIV96
厂商: INTERSIL CORP
元件分类: 无绳电话/电话
英文描述: Circular Connector; No. of Contacts:5; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-5 RoHS Compliant: No
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
封装: 7 X 7 X 1 MM, PLASTIC, TQFP-48
文件页数: 26/39页
文件大小: 251K
代理商: HFA3860AIV96
2-156
Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CR12
SQ1 CCA Thresh (high)
R/W
30
01
CR13
SQ1 CCA Thresh (low)
R/W
34
98
CR14
ED or RSSI Thresh
R/W
38
20
CR15
SFD Timer
R/W
3C
90
CR16
Signal Field (BPSK - 11 Chip Barker sequence)
R/W
40
0A
CR17
Signal Field (QPSK - 11 Chip Barker sequence)
R/W
44
14
CR18
Signal Field (BPSK - Mod Walsh sequence)
R/W
48
37
CR19
Signal Field (QPSK - Mod Walsh sequence)
R/W
4C
6E
CR20
TX Signal Field
R/W
50
00/01/02/03
CR21
TX Service Field
R/W
54
00
CR22
TX Length Field (high)
R/W
58
FF
CR23
TX Length Field (low)
R/W
5C
FF
CR24
RX Status
R
60
X
CR25
RX service Field Status
R
64
X
CR26
RX Length Field status (high)
R
68
X
CR27
RX Length Field status (low)
R
6C
X
CR28
Test Bus Address
R/W
70
00
CR29
Test Bus Monitor
R
74
X
CR30
Test Register 1
R/W
78
00
CR31
RX Control
R/W
7C
01
TABLE 11. CONTROL REGISTER VALUES FOR SINGLE ANTENNA ACQUISITION (Continued)
CONFIGURATION
REGISTER
NAME
TYPE
REGISTER
ADDRESS HEX
1/2/5.5/11MBps
CONFIGURATION REGISTER 0 ADDRESS (0h) PART/VERSION CODE
Bit 7:4
Part Code
0 = HFA3860A
Bit 3:0
Version Code
2 = Second Version
CONFIGURATION REGISTER 1 ADDRESS (04h) I/O POLARITY
This register is used to define the phase of clocks and other interface signals. 00h is normal setting.
Bit 7
This controls the phase of the RX_CLK output
Logic 1 = Invert Clk
Logic 0 = Non-Inverted Clk
Bit 6
This control bit selects the active level of the MD_RDY output pin 34.
Logic 1 = MD_RDY is Active 0
Logic 0 = MD_RDY is Active 1
Bit 5
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32.
Logic 1 = CCA Active 1
Logic 0 = CCA Active 0
Bit 4
This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 44.
Logic 1 = ED Active 0
Logic 0 = ED Active 1
HFA3860A
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