参数资料
型号: HFA3863IN
厂商: INTERSIL CORP
元件分类: 无绳电话/电话
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64
封装: 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64
文件页数: 16/39页
文件大小: 305K
代理商: HFA3863IN
4-16
Channel Matched Filter (CMF) Description
The receive section shown in Figure 13 operates on the
RAKE receiver principle which maximizes the SNR of the
signal by combining the energy of multipath signal
components. The RAKE receiver is implemented with a
Channel Matched Filter (CMF) using a FIR filter structure
with 16 taps. The CMF is programmed by calculating the
Channel Impulse Response (CIR) of the channel and
mathematically manipulating that to form the tap coefficients
of the CMF. Thus, the CMF is set to compensate the channel
characteristics that distort the signal. Since the calculation of
the CIR is inaccurate at low SNR or in the presence of strong
CW interference, the chip has thresholds (CR 36 to 39) that
are set to substitute a default CMF shape under those
conditions. This default CMF shape is designed to
compensate only the known transmit and receive non
linearity.
PN Correlators Description
There are two types of correlators in the HFA3863 baseband
processor. The first is a parallel matched filter correlator that
correlates for the Barker sequence used in preamble,
header, and PSK data modes. This Barker code correlator is
designed to handle BPSK spreading with carrier offsets up
to
±
50ppm and 11 chips per symbol. Since the spreading is
BPSK, the correlator is implemented with two real
PREAMBLE/HEADER
CRC-16
GENERATOR
TX_AGC_IN (18)
V
REF
(16)
I
REF
(21)
ANTSEL (39)
(60) CCA
TX_DATA
SCRAMBLER
(58) TXD
P
(52) RXCLK
MODULATOR,
BARKER/CCK
TXI (23, 24)
TXQ (29, 30)
TIMING
GENERATOR
MCLK
(12, 17, 22, 31)
V
DD
(ANALOG)
(2, 8, 37, 41, 57)
V
DD
(DIGITAL)
(9, 15, 20, 25, 28)
GND (ANALOG)
(1, 7, 36, 43, 56)
GND (DIGITAL)
(55) TXCLK
(59) TX_RDY
(62) TX_PE
ANTSEL (40)
(4) SCLK
(3) SD
(64) SDI
(5) R/W
(6) CS
S
P
T
P
(42)
MCLK
T
(45)
T
(44)
(46)
T
(47)
T
(48)
T
(49)
T
(50)
T
(51)
T
TEST PORT
FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
TX AGC
CONTROL
TRANSMIT
FILTER
O
T
O
DAC
DAC
TX
STATE
CONTROL
TX_IF_AGC (35)
6-BIT
DAC
REGISTER
6-BIT
ADC
HFA3863
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