参数资料
型号: HI-774
厂商: Intersil Corporation
英文描述: 128 MACROCELL 3.3 VOLT ISP CPLD
中文描述: 完成后,12位A / D转换器与微处理器接口
文件页数: 13/18页
文件大小: 200K
代理商: HI-774
6-964
Range Connections and Calibration Procedures
The HI-X74(A) is a “complete” A/D converter, meaning it is
fully operational with addition of the power supply voltages, a
Start Convert signal, and a few external components as
shown in Figure 2 and Figure 3. Nothing more is required for
most applications.
Whether controlled by a processor or operating in the stand-
alone mode, the HI-X74(A) offers four standard input ranges:
0V to +10V, 0V to +20V,
±
5V and
±
10V. The maximum errors
for gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Power supply and ground connections have been dis-
cussed in an earlier section.
Unipolar Connections and Calibration
Refer to Figure 2. The resistors shown (see Note) are for
calibration of offset and gain. If this is not required, replace
R2 with a 50
, 1% metal film resistor and remove the net-
work on pin 12. Connect pin 12 to pin 9. Then, connect the
analog signal to pin 13 for the 0V to 10V range, or to pin 14
for the 0V to 20V range. Inputs to +20V (5V over the power
supply) are no problem - the converter operates normally.
Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the mid-
point of an increment of analog input, as denoted by two
adjacent code changes. Nominal value of an increment is
one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an
adjustment is complete. Therefore, calibration is performed
in terms of the observable code changes instead of the
midpoint between code changes.
For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all 0’s. To do
this, apply an input of +
1
/
2
LSB (+1.22mV for the 10V range;
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.
Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 1
1
/
2
LSBs below the nominal full scale (+9.9963V for
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.
Bipolar Connections and Calibration
Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiome-
ters R1 and R2 (see Note). If this isn’t required, either or
both pots may be replaced by a 50
, 1% metal film resistor.
Connect the Analog signal to pin 13 for a
±
5V range, or to
pin 14 for a
±
10V range. Calibration of offset and gain is sim-
ilar to that for the unipolar ranges as discussed above. First
apply a DC input voltage
1
/
2
LSB above negative full scale
(i.e., -4.9988V for the
±
5V range, or -9.9976V for the
±
10V
range). Adjust the offset potentiometer R1 for flicker between
output codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage 1
1
/
2
LSBs below positive full scale
(+4.9963V for
±
5V range; +9.9927V for
±
10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111.
NOTE: The 100
potentiometer R2 provides Gain Adjust for the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 50
, 1% metal film resistor. Then, to pro-
vide Gain Adjust for the 10.24V range, add a 200
potentiometer in
series with pin 13. For the 20.48V range, add a 500
potentiometer
in series with pin 14.
Controlling the HI-X74(A)
The HI-X74(A) includes logic for direct interface to most
microprocessor systems. The processor may take full con-
trol of each conversion, or the converter may operate in the
“stand-alone” mode, controlled only by the R/C input. Full
control consists of selecting an 8-bit or 12-bit conversion
cycle, initiating the conversion, and reading the output data
when ready-choosing either 12 bits at once or 8 followed by
4, in a left-justified format. The five control inputs are all
TTL/CMOS-compatible: (12/8, CS, A
O
, R/C and CE). Table
1 illustrates the use of these inputs in controlling the
converter’s operations. Also, a simplified schematic of the
internal control logic is shown in Figure 7.
When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 3. BIPOLAR CONNECTIONS
16-19
LOW BITS
20-23
MIDDLE BITS
24-27
HIGH BITS
STS 28
+5V 1
+15V 7
-15V 11
DIG COM 15
GAIN
R2
100
100
±
5V
ANALOG
INPUTS
±
10V
OFFSET
10 REF IN
8
REF OUT
12 BIP OFF
13 10V
IN
14 20V
IN
9 ANA
COM
2 12/8
3
CS
4
A
O
5
R/C
6
CE
R1
HI-574A, HI-674A, HI-774
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