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参数资料
| 型号： | HI20201JCP |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | DAC |
| 英文描述： | 10-Bit, 160 MSPS, Ultra High Speed D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.0052 us SETTLING TIME, 10-BIT DAC, PDIP28 |
| 文件页数： | 4/11页 |
| 文件大小： | 82K |
| 代理商： | HI20201JCP |
10-1200
Timing Diagram
Pin Descriptions
POWER SUPPLY CHARACTERISITICS
I
EE
Power Dissipation
-60
-75
-90
mA
75
load
-
420
470
mW
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. Excludes error due to reference drift.
4. Electrical specifications guaranteed only under the stated operating conditions.
Electrical Specifications
T
A
= 25
o
C, AV
EE
= DV
EE
= -5.2V, AGND = DGND = 0V, R
L
=
∞
, V
OUT
= -1V
(Continued)
PARAMETER
TEST CONDITIONS
HI20201JCB/JCP
UNITS
MIN
TYP
MAX
28 PIN SOIC
PIN NAME
PIN DESCRIPTION
1-10
D0 (LSB)-D9 (MSB)
Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 9, the Most Significant Bit.
11, 12, 19, 21- 25
NC
No Connect, not used.
13
CLK
Negative Differential Clock Input.
14
CLK
Positive Differential Clock Input
15
DV
EE
Digital (ECL) Power Supply -4.75V to -7V.
16
COMPL
Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the
input buffer. When cleared to a (ECL) logic Low the input data is not complemented.
17
DV
SS
Digital Ground.
18
AV
SS
Analog Ground.
20
I
OUT
Current Output Pin.
26
AV
EE
Analog Supply -4.75V to -7V.
27
V
REF
Input Reference Voltage used to set the output full scale range.
28
AV
SS
Analog Ground.
CLK
CLK
DATA
0V
D/A OUT
-1V
90%
50%
10%
N + 1
N + 1
N
t
SU
t
HD
t
D
N
t
r
t
f
t
D
FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)
HI20201
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