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参数资料
| 型号： | HI20203JCP |
| 厂商： | INTERSIL CORP |
| 元件分类： | DAC |
| 英文描述： | 8-Bit, 160 MSPS, Ultra High-Speed D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.0043 us SETTLING TIME, 8-BIT DAC, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 4/10页 |
| 文件大小： | 80K |
| 代理商： | HI20203JCP |
10-4
Timing Diagram
Input Logic Current, I
IL
, I
IH
(For D9 thru D6, COMPL)
V
IH
= -0.89V, V
IL
= -1.75V
(Note 2)
0.1
1.5
6.0
μ
A
Input Logic Current, I
IL
, I
IH
(For D5 thru D0)
V
IH
= -0.89V, V
IL
= -1.75V
(Note 2)
0.1
0.75
3.0
μ
A
TIMING CHARACTERISTICS
Data Setup Time, t
SU
See Figure 11
5
-
-
ns
Data Hold Time, t
HLD
See Figure 11
1
-
-
ns
Propagation Delay Time, t
PD
See Figure 11
-
3.8
-
ns
Settling Time, t
SET
(to
1
/
2
LSB)
See Figure 11
-
4.3
-
ns
POWER SUPPLY CHARACTERISITICS
I
EE
-60
-75
-90
mA
Power Dissipation
75
load
-
420
470
mW
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. Excludes error due to reference drift.
4. Electrical specifications guaranteed only under the stated operating conditions.
Electrical Specifications
AV
EE
= -5.2V, DV
EE
= -5.2V, AGND = 0V, DGND = 0V, R
L
=
∞
, V
OUT
= -1V, T
A
= 25
o
C
(Continued)
PARAMETER
TEST CONDITION
HI20203JCB/JCP
UNITS
MIN
TYP
MAX
CLK
CLK
DATA
0V
D/A OUT
-1V
90%
50%
10%
N + 1
N + 1
N
t
SU
t
HD
t
D
N
t
r
t
f
t
D
FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)
HI20203
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相关代理商/技术参数 |
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