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参数资料
| 型号： | HI20203JCP |
| 厂商： | INTERSIL CORP |
| 元件分类： | DAC |
| 英文描述： | 8-Bit, 160 MSPS, Ultra High-Speed D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.0043 us SETTLING TIME, 8-BIT DAC, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 7/10页 |
| 文件大小： | 80K |
| 代理商： | HI20203JCP |
10-7
Variable Attenuator Capability
The HI20203 can be used in a multiplying mode with a variable
frequency input on the V
REF
pin. In order for the part to operate
correctly a DC bias must be applied and the incoming AC sig-
nal should be coupled to the V
REF
pin. See Figure 13 for the
application circuit. The user must first adjust the DC reference
voltage. The incoming signal must be attenuated so as not to
exceed the maximum (+1.4V) and minimum (+0.5V) reference
input. The typical output Small Signal Bandwidth is 14MHz.
Integral Linearity
The Integral Linearity is measured using the End Point
method. In the End Point method the gain is adjusted. A line
is then established from the zero point to the end point or
Full Scale of the converter. All codes along the transfer curve
must fall within an error band of 1 LSB of the line. Figure 10
shows the linearity test circuit.
Differential Linearity
The Differential Linearity is the difference from the ideal step.
To guarantee monotonicity a maximum of 1 LSB differential
error is allowed. When more than 1 LSB is specified the con-
verter is considered to be missing codes. Figure 10 shows
the linearity test circuit.
Clock Phase Relationship
The HI20203 is designed to be operated at very high speed
(i.e., 160MHz). The clock lines should be driven with
ECL100K logic for full performance. Any external data
drivers and clock drivers should be terminated with 50
to
minimize reflections and ringing.
Internal Data Register
The HI20203 incorporates a data register as shown in the
Functional Block Diagram. This register is updated on the
rising edge of the CLK line. The state of the Complement bit
(COMPL) will determine the data coding. See Table 2.
Thermal Considerations
The temperature coefficient of the full scale output voltage
and zero offset voltage depend on the load resistance con-
nected to I
OUT
. The larger the load resistor the better (i.e.,
smaller) the temperature coefficient of the D/A. See Figure 3
in the performance curves section.
Noise Reduction
Digital switching noise must be minimized to guarantee system
specifications. Since 1 LSB corresponds to 1mV for 10-bit
resolution, care must be taken in the layout of a circuit board.
Separate ground planes should be used for DV
SS
and
AV
SS
. They should be connected back at the power supply.
Separate power planes should be used for DV
EE
and AV
EE
.
They should be decoupled with a 1
μ
F tantalum capacitor
and a ceramic 0.047
μ
F capacitor positioned as close to the
body of the IC as possible.
TABLE 2. INPUT CODING TABLE
INPUT CODE
OUTPUT CODE
COMPL = 1
COMPL = 0
00 0000 0000
0
-1
10 0000 0000
-0.5
-0.5
11 1111 1111
-1
0
Test Circuits and Waveforms
FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
a
b
a
b
a
b
a
b
a
b
a
b
a
b
a
b
S1
S2
S3
S4
S5
S6
S7
S8
-0.89V OR
-1.75V
a
b
a
b
S12
a
S14
b
a
S15
b
-1.75V
I
3
S13
I
4
-0.89V
a
b
S11
-1.75V
-0.89V
I
2
a
b
a
b
S20
S16
a
b
I
6
I
1
5.2V
4.56V
a
b
S17
a
b
S18
I
5
5.2V
a
b
S19
V1
1mA
HI20203
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|---|---|
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HI20203JPC | 制造商:Harris Corporation 功能描述: |
| HI20206 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter |
| HI20206JCP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
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| HI2-0300-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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