参数资料
型号: HI5628EVAL1
厂商: Intersil
文件页数: 6/12页
文件大小: 0K
描述: EVALUATION BOARD FOR LQFPHI5628
标准包装: 1
DAC 的数量: 2
位数: 8
采样率(每秒): 125M
数据接口: 并联
设置时间: 15ns
DAC 型: 电流
工作温度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: HI5628
Application Note 9840
Appendix B Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
39-32
QD7 (MSB) Through Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
QD0 (LSB)
channel.
1-5, 48-46
8
15
23
22
14, 24
13, 18, 19, 25
17
16
20
21
11, 27
12, 26
6, 7, 10, 28, 30,
31, 41, 44
9, 29, 40, 45
43
42
ID7 (MSB) Through
ID0 (LSB)
SLEEP
REFLO
REFIO
FSADJ
ICOMP1, QCOMP1
AGND
IOUTB
IOUTA
QOUTB
QOUTA
NC
AV DD
DGND
DV DD
ICLK
QCLK
6
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20 μ A active pulldown current.
Connect to analog ground to enable internal 1.2V reference or connect to AV DD to disable.
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1 μ F cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x I FSADJ .
For use in reducing bandwidth/noise of the I and Q channels. Recommended: connect 0.1 μ F to AV DD
as close as possible to each of the pins. These two pins MUST be connected together externally.
Analog Ground Connections.
The complementary current output of the I Channel. Bits set to all 0s gives full scale current.
Current output of the I channel. Bits set to all 1s gives full scale current.
The complementary current output of the Q Channel. Bits set to all 0s gives full scale current.
Current output of the Q Channel. Bits set to all 1s gives full scale current.
No Connect. Recommended: Connect to ground.
Analog Supply (+2.7V to +5.5V).
Digital Ground.
Supply voltage for digital circuitry (+2.7V to +5.5V).
Clock input for I Channel. Positive edge of clock latches data.
Clock input for Q Channel. Positive edge of clock latches data.
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