参数资料
型号: HI5731-EVS
厂商: Intersil
文件页数: 1/10页
文件大小: 0K
描述: EVALUATION PLATFORM SOIC HI5731
标准包装: 1
DAC 的数量: 1
位数: 12
采样率(每秒): 100M
数据接口: 并联
设置时间: 20ns
DAC 型: 电流
工作温度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: HI5731
Using The HI5731 Evaluation Module
TM
Introduction
Application Note
March 1999
AN9602.1
The HI5731 is a 12 bit 100MHz Digital to Analog Converter.
This current out DAC is designed for low glitch and high
Spurious Free Dynamic Range operation. As a result, this
DAC is ideally suited for Signal Reconstruction and DDS
(Direct Digital Synthesis) applications due to its inherent low
noise design.
Architecture
The HI5731 DAC is designed with a split architecture to
minimize glitch while maximizing linearity. Figure 1 shows
the functional architecture of the device. The 8 least
signi?cant bits of the converter are derived by a traditional
R/2R network to binarily weight the 1.28mA (nominal)
current sources. The upper 4, or most signi?cant bits, are
implemented as segmented or thermometer decoded
current sources. The thermometer decoder converts the
incoming 4 bits to 15 control lines to enable the most
signi?cant current sources.
As shown in Figure 2 the thermometer decoder translates
the 4 bit binary input data into a decode that enables
individual current sources. For example a binary code of
0110 on the data bits D8 through D11 will enable current
sources I1, I2, I3, I4, I5, and I6. The thermometer decoding
architecture ensures good differential non-linearity, which is
further enhanced by the addition of laser trimming. Also,
compared to a straight R/2R design, the worst case glitch is
greatly reduced since creating the MSB current is the sum of
current sources I1 through I8. Overall glitch is therefore
reduced by a factor of 16. This also reduces the theoretical
switching skew from current source to current source by
using identically sized switches with identical gain, leakage,
and transient responses.
(LSB) D0
D1
D2
D3
D4
8 LSBs
CURRENT
CELLS
R/2R
NETWORK
D5
D6
12-BIT
MASTER
REGISTER
DATA
BUFFER/
LEVEL
SHIFTER
SLAVE
REGISTER
D7
D8
D9
D10
(MSB) D11
UPPER
4-BIT
DECODER
15
SWITCHED
CURRENT
CELLS
I OUT
I OUT
REF CELL
CLK
CTRL AMP
OVERDRIVEABLE
VOLTAGE
+
-
25 ?
IN
CTRL AMP
OUT
REFERENCE
AV EE
AGND
DV EE
DGND
V CC
REF OUT
R SET
FIGURE 1. HI5731 BLOCK DIAGRAM
3-1
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright
? Intersil Corporation 2000
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