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参数资料
| 型号： | HI5731-EVS |
| 厂商： | Intersil |
| 文件页数： | 2/10页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM SOIC HI5731 |
| 标准包装： | 1 |
| DAC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 100M |
| 数据接口： | 并联 |
| 设置时间： | 20ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | HI5731 |
Application Note 9602
BIT 11 (MSB)
BIT 10
I15
I14
I13
V
GLITCH AREA = 1/2 (H X W)
HEIGHT (H)
BIT 9
I12
WIDTH (W)
t(ps)
I11
FIGURE 3. GLITCH AREA
BIT 8
4-BIT BINARY
TO
THERMOMETER
DECODER
I10
I9
I8
I7
I6
I5
Input Timing/Logic Levels
The HI5731 has a maximum clock rate speci?cation of
100MHz. The data setup time before the 50% point of the
rising edge of the clock is t S = 3ns (Min) and the hold time is
t H = 0.5ns (Min). Logic levels are 0.8V (Max) for an input low
and 2.0V (Min) for a logic high. The HI5731 is both TTL and
CMOS input compatible.
D11 - D0
I4
CLK
I3
I2
t S
t H
I1
SUMMING
JUNCTION (I OUT )
FIGURE 2. THERMOMETER DECODER
Designing to Minimize Glitch
One cause of Glitch is the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time. Unequal delay paths through the
device can cause one current source which is to change
before another. To minimize this, the Intersil HI5731
employes an internal register just prior to the current sources
which is updated on the rising clock edge. In traditional
DACs the worst case glitch usually happens at the major
transition i.e., 0111 1111 1111 to 1000 0000 0000. But in the
HI5731 the worst case glitch is moved to the 0000 1111
1111 to 1111 000 0000 transition. This is achieved by the
split R/2R segmented current source architecture. This
decreases the amount of current switching at any one time
and reduces the glitch by a factor of 16.
Since the glitch is a transient event, this leads designers to
believe that a simple low pass ?lter can be used to eliminate
or reduce the size of the glitch. In effect low pass ?ltering a
glitch tends to “smear” the event and does little to remove
the energy of the transient.
3-2
FIGURE 4. HI5731 DATA TIMING
Integral Linearity
The HI5731 has an FSR range of 20.48mA. When driving a
50 ? load the full scale voltage swing is 0V to +0.84V (due to
the internal 227 ? ladder resistance in parallel with the 50 ?
load). Most video and communication applications use a
1V P-P voltage swing which yields 20.48mA full scale current
sink capability. With a 1V P-P voltage swing on the HI5731
output an LSB is:
LSB = Full Scale Range/(2 N -1)
where N is the number of bits and the Full Scale Range is
1V P-P .
The LSB size for this application is.02mV. To determine the
Integral Linearity of the HI5731 the bit weights of each major
transition is taken. The Best Fit Straight Line method is used
to calculate the overall INL. Measurements are taken at bits
0 through 6 at each bit transition. Then all combinations of
the upper 4 bits are measured. Finally some worst case
codes are measured and the full scale is measured. Once
this is completed a best ?t straight line is drawn through the
data points and the worst case deviation is determined.
The worst case integral linearity of the HI5731 is speci?ed to
be less than 1.5 LSB. The implementation of laser trim
assures 12-bit match from current cell to current cell. Figure
5 graphically illustrates the typical linearity performance of
the HI5731.
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| HI5762EVAL2 | EVALUATION MOD FOR HI5762 AMP |
| HI5767EVAL1 | EVALUATION PLATFORM HI5767 |
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