参数资料
| 型号： | HI5662/6IN |
| 厂商： | Intersil |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | ADC DUAL 8-BIT 60MSPS 44-MQFP |
| 标准包装： | 96 |
| 位数： | 8 |
| 采样率（每秒）： | 60M |
| 数据接口： | 并联 |
| 功率耗散（最大）： | 670mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，双极 |
3-13
or below AGND. In this case, VDC could range between 0.5V
and 4.5V without a significant change in ADC performance.
The simplest way to produce VDC is to use the DC bias source,
I/QVDC, of the HI5662.
The single ended analog input can be DC coupled
(Figure 18) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 18 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/QIN+ to I/QIN- will help lter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufcient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is rst converted to differential before
driving the HI5662.
Sampling Clock Requirements
The HI5662 sampling clock input provides a standard high-
speed interface to external TTL/CMOS logic families.
In order to ensure rated performance of the HI5662, the duty
cycle of the clock should be held at 50%
±5%. It must also
have low jitter and operate at standard TTL/CMOS levels.
Performance of the HI5662 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is rst applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must to be performed
before valid data is available.
Supply and Ground Considerations
The HI5662 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The
digital data outputs also have a separate supply pin, DVCC3,
which can be powered from a 3.0V or 5.0V supply. This allows
the outputs to interface with 3.0V logic if so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5662 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Denitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4LSB
above half-scale. Offset is dened as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4LSB below Positive Full Scale (+FS) with the offset
error removed. Full scale error is dened as the deviation of
the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
t straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Denitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5662. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is typically -0.5dB down from full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
The Effective Number of Bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
where: VCORR = 0.5dB (Typical).
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is backed off from full scale.
I/QIN+
I/QIN-
HI5662
VDC
R
C
VIN
VDC
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
HI5662
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HI5662EVAL2 | 功能描述:数据转换 IC 开发工具 HI5662 EVAL PL ATFORM RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| HI5662IN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Converter IC |
| HI5667 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:8-Bit, 60MSPS A/D Converter with Internal Voltage Reference |
| HI5667/6CA | 制造商:Rochester Electronics LLC 功能描述:A/D, 8-BIT,60MSPS,COM TEMP,28 SSOP,TTL/CMOS (HI5767/6, 10- - Bulk |
| HI5667/6CB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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