参数资料
| 型号： | HI5662/6IN |
| 厂商： | Intersil |
| 文件页数： | 6/14页 |
| 文件大小： | 0K |
| 描述： | ADC DUAL 8-BIT 60MSPS 44-MQFP |
| 标准包装： | 96 |
| 位数： | 8 |
| 采样率（每秒）： | 60M |
| 数据接口： | 并联 |
| 功率耗散（最大）： | 670mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，双极 |
3-14
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS sum
of all the other spectral components below the Nyquist
frequency, fS/2, excluding DC.
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise at
a specied input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS/2
excluding the fundamental, the rst ve harmonics and DC.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spectral component in the
spectrum below fS/2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2, are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB
below full scale.
Transient Response
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
Over-Voltage Recovery
Over-Voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specied sampling frequency.
I/Q Channel Crosstalk
I/Q Channel Crosstalk is a measure of the amount of
channel separation or isolation between the two A/D
converter cores contained within the dual converter
package. The measurement consists of stimulating one
channel of the converter with a fullscale input signal and
then measuring the amount that signal is below, in dBc, a
fullscale signal on the opposite channel.
Timing Denitions
Refer to Figure 1 and Figure 2 for these denitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data
representing an analog input sample is output to the digital
data bus following the 6th cycle of the clock after the analog
sample is taken. This is due to the pipeline nature of the
converter where the analog sample has to ripple through the
internal subconverter stages. This delay is specied as the
data latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 6 sample clock cycles.
Power-Up Initialization
This time is dened as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
HI5662
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| HI5662EVAL2 | 功能描述:数据转换 IC 开发工具 HI5662 EVAL PL ATFORM RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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| HI5667/6CA | 制造商:Rochester Electronics LLC 功能描述:A/D, 8-BIT,60MSPS,COM TEMP,28 SSOP,TTL/CMOS (HI5767/6, 10- - Bulk |
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