参数资料
型号: HI5662EVAL2
厂商: Intersil
文件页数: 3/17页
文件大小: 0K
描述: EVALUATION PLATFORM HI5662
标准包装: 1
ADC 的数量: 2
位数: 8
采样率(每秒): 60M
数据接口: 并联
输入范围: 1 Vpp
在以下条件下的电源(标准): 650mW @ 600MSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: HI5662
已供物品:
Application Note 9823
Figure 2 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK) and
analog input (V IN ) signals are sourced from low phase noise
HP8662A synthesized signal generators that are phase
locked to each other to ensure coherence. The output of the
HP8662A
REF
HP8662A
BANDPASS
FILTER
signal generator driving the ADC analog input is bandpass
?ltered to improve the harmonic distortion of the analog input
signal. The comparator on the evaluation board will convert
CLK
V IN
EVALUATION BOARD
the sine wave CLK input signal to a square wave at TTL logic
levels to drive the sample clock input of the HI5662. The
ADC data is captured by a logic analyzer and then
transferred over the GPIB bus to the PC. The PC has the
required software to perform the Fast Fourier Transform
(FFT) and do the data analysis.
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship: F I /F S
= M/N, where F I is the frequency of the input analog
sinusoid, F S is the sampling frequency, N is the number of
samples, and M is the number of cycles over which the
samples are taken. By making M an integer and odd number
(1, 3, 5, ...) the samples are assured of being nonrepetitive.
Refer to the HI5662 data sheet for a complete list of test
de?nitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
SINEWAVE CLK IN
(J3)
t PD1
HI5662 SAMPLE
CLOCK INPUT
COMPARATOR
I_IN/Q_IN
CLK HI5662
I/Q DIGITAL DATA OUTPUT
HI5662EVAL2
8
DATA ACQUISITION SYSTEM
GPIB
PC
FIGURE 1. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM
(CLK AT U7-2)
t OD
HI5662 DIGITAL
DATA OUTPUT
DATA N-1
DATA N
DATA N+1
(D0 - D13)
CLOCK OUT
(CLK AT U10,U11, P1-12 AND P2-12)
t PD2
DIGITAL DATA OUTPUTS
(74FCT2821)
DATA N-1
DATA N
FIGURE 2. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS (TYPICAL)
3-3
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