参数资料
型号: HI5762EVAL2
厂商: Intersil Corporation
英文描述: Dual 10-Bit, 60MSPS A/D Converter with Internal Voltage Reference
中文描述: 双10位,60MSPS的A / D转换器内部电压基准
文件页数: 14/14页
文件大小: 133K
代理商: HI5762EVAL2
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
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1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
I/Q Channel Crosstalk
I/Q Channel Crosstalk is a measure of the amount of
channel separation or isolation between the two A/D
converter cores contained within the dual converter
package. The measurement consists of stimulating one
channel of the converter with a fullscale input signal and
then measuring the amount that signal is below, in dBc, a
fullscale signal on the opposite channel.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (t
AP
)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
AJ
)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
H
)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
OD
)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
LAT
)
After the analog sample is taken, the digital data representing
an analog input sample is output to the digital data bus
following the 6th cycle of the clock after the analog sample is
taken. This is due to the pipeline nature of the converter
where the analog sample has to ripple through the internal
subconverter stages. This delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 6 sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
HI5762
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