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参数资料
| 型号： | HI7190IP |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | null24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP20 |
| 封装： | PLASTIC, MS-001AD, DIP-20 |
| 文件页数： | 8/24页 |
| 文件大小： | 187K |
| 代理商： | HI7190IP |
1878
Definitions
Integral Non-Linearity, INL,
is the maximum deviation of
any digital code from a straight line passing through the end-
points of the transfer function. The endpoints of the transfer
function are zero scale (a point 0.5 LSB below the first code
transition 000...000 and 000...001) and full scale (a point 0.5
LSB above the last code transition 111...110 to 111...111).
Differential Non-Linearity, DNL,
is the deviation from the
actual difference between midpoints and the ideal difference
between midpoints (1 LSB) for adjacent codes. If this differ-
ence is equal to or more negative than 1 LSB, a code will be
missed.
Offset Error, V
OS
,
is the deviation of the first code transition
from the ideal input voltage (V
IN
- 0.5 LSB). This error can
be calibrated to the order of the noise level shown in Table 1.
Full Scale Error, FSE,
is the deviation of the last code
transition from the ideal input full scale
(V
IN
- + V
REF
/Gain - 1.5 LSB). This error can be calibrated
to the order of the noise level shown in Table 1.
voltage
Input Span,
defines the minimum and maximum input
voltages the device can handle while still calibrating properly
for gain.
Noise, e
N
,
Table 1 shows the peak-to-peak and RMS noise
for typical notch and -3dB frequencies. The device program-
ming was for bipolar input with a V
REF
of +2.5V. This implies
the input range is 5V. The analysis was performed on 100
conversions with the peak-to-peak output noise being the
difference between the maximum and minimum readings
over a rolling 10 conversion window. The equation to convert
the peak-to-peak noise data to ENOB is:
ENOB = Log
2
(V
FS
/ V
NRMS
)
where: V
FS
= 5V, V
NRMS
= V
NP-P
/ CF and
CF = 6.6 (Imperical Crest Factor)
The noise from the part comes from two sources, the
quantization noise from the analog-to-digital conversion pro-
cess and device noise. Device noise (or Wideband Noise) is
independent of gain and essentially flat across the frequency
spectrum. Quantization noise is ratiometric to input full scale
(and hence gain) and its frequency response is shaped by
the modulator.
Looking at Table 1, as the cutoff frequency increases the
output noise increases. This is due to more of the
quantization noise of the part coming through to the output
and, hence, the output noise increases with increasing -
3dB frequencies. For the lower notch settings, the output
noise is dominated by the device noise and, hence, altering
the gain has little effect on the output noise. At higher notch
frequencies, the quantization noise dominates the output
noise and, in this case, the output noise tends to decrease
with increasing gain.
Since the output noise comes from two sources, the effective
resolution of the device (i.e., the ratio of the input full scale to
the output RMS noise) does not remain constant with
increasing gain or with increasing bandwidth. It is possible to
do post-filtering (such as brick wall filtering) on the data to
improve the overall resolution for a given -3dB frequency and
also to further reduce the output noise.
Circuit Description
The HI7190 is a monolithic, sigma delta A/D converter which
operates from
±
5V
supplies and is intended for
measurement of wide dynamic range, low frequency signals.
It contains a Programmable Gain Instrumentation Amplifier
(PGIA), sigma delta ADC, digital filter, bidirectional serial
port (compatible with many industry standard protocols),
clock oscillator, and an on-chip controller.
The signal and reference inputs are fully differential for
maximum flexibility and performance. Normally V
RHI
and
V
RLO
are tied to +2.5V and AGND respectively. This allows
for input ranges of 2.5V and 5V when operating in the unipo-
lar and bipolar modes respectively (assuming the PGIA is
configured for a gain of 1). The internal PGIA provides input
gains from 1 to 128 and eliminates the need for external pre-
amplifiers. This means the device will convert signals rang-
ing from 0V to +20mV and 0V to +2.5V when operating in
the unipolar mode or signals in the range of
±
20mV to
±
2.5V
when operating in the bipolar mode.
The input signal is continuously sampled at the input to the
HI7190 at a clock rate set by the oscillator frequency and the
selected gain. This signal then passes through the sigma
delta modulator (which includes the PGIA) and emerges as
a pulse train whose code density contains the analog signal
information. The output of the modulator is fed into the sinc
3
digital low pass filter. The filter output passes into the
calibration block where offset and gain errors are removed.
The calibrated data is then coded (2’s complement, offset
binary or binary) before being stored in the Data Output
Register. The Data Output Register update rate is deter-
mined by the first notch frequency of the digital filter. This
first notch frequency is programmed into HI7190 via the
Control Register and has a range of 10Hz to 1.953kHz which
corresponds to -3dB frequencies of 2.62Hz and 512Hz
respectively.
Output data coding on the HI7190 is programmable via the
Control Register. When operating in bipolar mode, data out-
put can be either 2’s complement or offset binary. In unipolar
mode output is binary.
The DRDY signal is used to alert the user that new output
data is available. Converted data is read via the HI7190
serial I/O port which is compatible with most synchronous
transfer formats including both the Motorola 6805/11 series
SPI and Intel 8051 series SSR protocols. Data Integrity is
always maintained at the HI7190 output port. This means
that if a data read of conversion N is begun but not finished
before the next conversion (conversion N + 1) is complete,
the DRDY line remains active (low) and the data being read
is not overwritten.
The HI7190 provides many calibration modes that can be
initiated at any time by writing to the Control Register. The
device can perform system calibration where external com-
ponents are included with the HI7190 in the calibration loop
HI7190
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HI7190IPZ | 功能描述:模数转换器 - ADC W/ANNEAL ADC 24BIT 1 0HZ SIGMADELTA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| HI7191 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191_06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7191IB | 功能描述:IC ADC 24BIT PROGBL SER 20-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| HI7191IBZ | 功能描述:模数转换器 - ADC ADC 24BIT SIGMADELTA 20 IND RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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