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参数资料
| 型号： | HIP1012ACBZA-T |
| 厂商： | Intersil |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC CTRLRL HOT PLUG DUAL 14-SOIC |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 10.5 V ~ 13.2 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 带卷 (TR) |
HIP1012A
Pin Descriptions
PIN #
1
SYMBOL
3V/12VS
FUNCTION
3.3 V/12V Source
DESCRIPTION
Connect to source of associated external N-Channel MOSFET switch to sense output
voltage.
2
3V/12VG
3.3V/12V Gate
Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node
to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 17.4V by a 10 μ A
current source when in 5v/12V mode of operation, otherwise capacitor will be charged to
11.4V. A small resistor (10 - 200 ? ) should be placed in series with the gate capacitor to
ground to prevent current oscillations.
3
4
V DD
MODE/
PWRON1
Chip Supply
Power ON/ Reset
Invokes 3.3V operation
Connect to 12V supply. This can be either connected directly to the +12V rail supplying the
load voltage or to a dedicated V DD +12V supply. If the former is chosen special attention to
V DD decoupling must be paid.
PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on when
either pin is driven low. After a current limit time out, the chip is reset by the rising edge of a
3.3V control operation in preference to +12V control. By tying pin 4 to pin 3 the charge pump
5
PWRON2
when shorted to V DD , pin 3. reset signal applied to either PWRON pin. Each input has 100 μ A pul l up capability which is
compatible with 3V and 5V open drain and standard logic. PWRON1 is also used to invoke
Power ON/ Reset
is disabled and the UV threshold also shifts to 2.8V.
6
5VG
5V Gate
Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a 10 μ A
current source. A small resistor (10 - 200 ? ) should be placed in series with the gate
capacitor to ground to prevent current oscillations.
7
5VS
5V Source
Connect to the source side of 5V external N-Channel MOSFET switch to sense output
voltage.
8
5VISEN
5V Current Sense
Connect to the load side of the 5V sense resistor to measure the voltage drop across this
resistor between 5VS and 5VISEN pins.
9
PGOOD
Power Good indicator
Indicates that all output voltages are within specification. PGOOD is driven by an open drain
N-Channel MOSFET. It is pulled low when any output is not within specification.
10
C TIM
Current Limit Timing
Capacitor
Connect a capacitor from this pin to ground. This capacitor controls the time between the
onset of current limit and chip shutdown (current limit time-out). The duration of current limit
time-out (in seconds) = 200k ? x C TIM (Farads).
11
12
13
14
C PUMP
GND
R ILIM
3V/12VISEN
Charge Pump
Capacitor
Chip Ground
Current Limit Set
Resistor
3.3V/12V Current Sense
Connect a 0.1 μ F capacitor between this pin and V DD (pin3). Directly connect this pin to V DD
when in 3.3V control mode.
A resistor connected between this pin and ground determines the current level at which
current limit is activated. This current is determined by the ratio of the R ILIM resistor to the
sense resistor (R SENSE ). The current at current limit onset is equal to 10 μ A x (R ILIM /
R SENSE ).
Connect to the load side of sense resistor to measure the voltage drop across this resistor.
3
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