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参数资料
| 型号： | HIP2030 |
| 厂商： | Intersil Corporation |
| 英文描述： | 30V MCT/IGBT Gate Driver(MOS可控硅晶体管/绝缘栅双极晶体管门驱动器) |
| 中文描述： | 30V的海运码头/ IGBT栅极驱动器（马鞍山可控硅晶体管/绝缘栅双极晶体管门驱动器） |
| 文件页数： | 7/10页 |
| 文件大小： | 94K |
| 代理商： | HIP2030 |
7
HIP2030
FIGURE 4. INTERSIL HIP2030 EVALUATION BOARD
(NOTE 9)
NOTES:
1. Capacitors C5 and C6 are special function components which control MLT and MHT.
2. Asymmetrical gate drive may be obtained by opening J2 and adjusting R1 and R2 for the desired voltage ratio.
3. Insert C7 for charge pump operation.
4. Open J3 to disable the charge pump oscillator.
5. Open J1 to disable the internal 12V regulator.
6. R5 is added for noise rejection at high Cdv/dts.
7. The internal 5V reference (REF) must be operational for MHT and MLT functions to work properly.
8. P1 - P12 are access pads for all comparator inputs.
9. Request Intersil File #3918 for a full description of the HIP2030EVAL board.
P0
C5
C6
R2
C2
10
μ
F
C7
R3
1K
R4
1K
JP1
JP2
C4
47pF
R6
510
R13
R14
R11
10
R8
10
R12
J1
G
MOS GATE
GR
P+
P0
P
-
30VDC
J2
J3
5V INPUT
SIGNAL
-
+
R9
820
8
7
6
5
4
3
2
1
TLP2601
R1
C1 10.0
P1
P2
P3
P4
P5
P7
P9
U2
R10
R5
100
P
-
PO
0.10
P+
JP3
GO
P0
POS
CPA
CLMP
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18
R
19
20
21
22
23
24
25
26
27
28
B2+
L
-
P6
L+
R
-
B2
-
G-
R+
B
B
A
A
P
N
G
M
P
C
N
M
U1
HIP2030
P11
P8
P10
P12
BO
AO
LO
C3
R7
1K
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