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参数资料
| 型号： | HIP2100IBT |
| 厂商： | Intersil |
| 文件页数： | 12/12页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER HALF-BRIDGE 8-SOIC |
| 标准包装： | 2,500 |
| 配置： | 半桥 |
| 输入类型： | PWM |
| 延迟时间： | 20ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 114V |
| 电源电压： | 9 V ~ 14 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
HIP2100
Small Outline Exposed Pad Plastic Packages (EPSOIC)
N
INDEX
AREA
E
H
0.25(0.010) M
B M
M8.15C
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INCHES MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
1
2
3
A
A1
0.056
0.001
0.066
0.005
1.43
0.03
1.68
0.13
-
-
TOP VIEW
SEATING PLANE
L
B
C
D
E
0.0138
0.0075
0.189
0.150
0.0192
0.0098
0.196
0.157
0.35
0.19
4.80
3.811
0.49
0.25
4.98
3.99
9
-
3
4
-A-
D
A
h x 45°
e
H
0.050 BSC
0.230
0.244
1.27 BSC
5.84
6.20
-
-
e
B
0.25(0.010) M
-C-
C A M B S
A1
α
0.10(0.004)
C
h
L
N
α
P
0.010
0.016
0°
-
8
0.016
0.035
8°
0.126
0.25
0.41
0°
-
8
0.41
0.89
8°
3.200
5
6
7
-
11
SIDE VIEW
P1
-
0.099
-
2.514
11
Rev. 1 6/05
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
N
P
BOTTOM VIEW
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN4022.14
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