参数资料
型号: HIP2101IBT
厂商: Intersil
文件页数: 11/12页
文件大小: 0K
描述: IC DRIVER HALF-BRIDGE 8-SOIC
标准包装: 2,500
配置: 半桥
输入类型: PWM
延迟时间: 25ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 100V
电源电压: 9 V ~ 14 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
HIP2101
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
H
0.25(0.010) M
B M
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
1
2
3
L
A
A1
0.0532
0.0040
0.0688
0.0098
1.35
0.10
1.75
0.25
-
-
SEATING PLANE
B
0.013
0.020
0.33
0.51
9
-A-
D
A
h x 45 o
C
D
0.0075
0.1890
0.0098
0.1968
0.19
4.80
0.25
5.00
-
3
-C-
μ α
E
e
0.1497 0.1574
0.050 BSC
3.80 4.00
1.27 BSC
4
-
e
B
A1
0.10(0.004)
C
H
h
0.2284
0.0099
0.2440
0.0196
5.80
0.25
6.20
0.50
-
5
0.25(0.010) M
C A M
B S
L
0.016
0.050
0.40
1.27
6
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
N
α
0 o
8
8 o
0 o
8
8 o
7
-
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
11
Rev. 0 12/93
FN9025.8
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