参数资料
型号: HIP2123FRTAZ
厂商: Intersil
文件页数: 3/16页
文件大小: 0K
描述: IC INTERFACE
标准包装: 75
系列: *
HIP2122, HIP2123
Pin Descriptions
9 LD TDFN 10 LD TDFN SYMBOL
DESCRIPTION
1
3
1
2
VDD
HB
Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to VSS.
High-side bootstrap supply voltage referenced to HS. Connect the positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
4
5
3
4
HO
HS
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of
bootstrap capacitor to this pin.
8
7
9
10
-
6
8
7
9
10
5
6
LI
HI
VSS
LO
NC
RDT
Low side driver input. For LI = 1, LO = 1 after programmed delay time; for LI = 0, LO = 0 with minimal delay.
High side driver input. For HI = 1, HO = 1 after programmed delay time; for Hi = 0, HO = 0 with minimal delay.
Negative supply input, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No Connect. This pin is isolated from all other pins.
A resistor connected between this pin and VSS adds additional delay time to the normal rising edge propagation
delay.
-
-
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Ordering Information
PART NUMBER
PART
TEMP. RANGE
PACKAGE
PKG.
(Notes 1, 2, 4)
HIP2122FRTAZ
HIP2123FRTAZ
HIP2122FRTBZ (Note 3)
HIP2123FRTBZ (Note 3)
MARKING
HIP 2122AZ
HIP 2123AZ
HIP 2122BZ
HIP 2123BZ
INPUT
CMOS
3.3V/TTL
CMOS
3.3V/TTL
(°C)
- 40 to +125
- 40 to +125
- 40 to +125
- 40 to +125
(Pb-Free)
10 Ld 4x4 TDFN
10 Ld 4x4 TDFN
9 Ld 4x4 TDFN
9 Ld 4x4 TDFN
DWG. #
L10.4x4
L10.4x4
L9.4x4
L9.4x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
PbHfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing.
4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2122 , HIP2123 . For more information on MSL please see tech brief
TB363 .
3
FN7670.0
December 23, 2011
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