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参数资料
| 型号： | HIP4086AP |
| 厂商： | Intersil |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER 3-PHASE FET 24-PDIP |
| 标准包装： | 15 |
| 配置： | 3 相桥 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 65ns |
| 电流 - 峰： | 500mA |
| 配置数： | 1 |
| 输出数： | 3 |
| 高端电压 - 最大（自引导启动）： | 95V |
| 电源电压： | 7 V ~ 15 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 24-PDIP |
| 包装： | 管件 |
HIP4086, HIP4086A
General PCB Layout Guidelines
The AC performance of the HIP4086/A depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance:
? Place the driver as close as possible to the driven power FETs.
? Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
? Keep power loops as short as possible by paralleling the
source and return traces.
? Use planes where practical; they are usually more effective
than parallel traces.
? Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
? When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10k ? resistor, is
10x larger than the noise on a 1k ? resistor.
? Be aware of magnetic fields emanating from motors,
transformers and inductors. Gaps in these magnetic structures
are especially bad for emitting flux.
? If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
? The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
? Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
13
? It may be necessary to add resistance to dampen resonating
parasitic circuits especially on xHO and xLO. If an external gate
resistor is unacceptable, then the layout must be improved to
minimize lead inductance.
? Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the HIP4086/A.
? Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
? Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
? Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated. This must be accounted for in the PCB
layout and circuit design.
? If you simulate your circuits, consider including parasitic
components especially parasitic lead inductance.
FN4220.9
February 1, 2013
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相关代理商/技术参数 |
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|---|---|
| HIP4086APZ | 功能描述:功率驱动器IC 80V 1.25A 3 PHS FL W V DRVR RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| HIP4086DEMO1Z | 制造商:Intersil Corporation 功能描述:DEMO BOARD 1 - 24LD SOIC - ROHS COMPLIANT - Bulk 制造商:Intersil Corporation 功能描述:BOARD EVAL FOR HIP4086 |
| HIP4086EVAL | 功能描述:EVALUATION BOARD GP HIP4086 RoHS:否 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器 嵌入式:否 已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池 次要属性:状态 LED 已供物品:板 |
| HIP5010 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:7V, 17A SynchroFET⑩ Complementary Drive Synchronous Half-Bridge |
| HIP5010IB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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