参数资料
型号: HIP6004DCBZ
厂商: Intersil
文件页数: 11/14页
文件大小: 0K
描述: IC CTRLR PWM VOLTAGE MON 20-SOIC
标准包装: 380
应用: 控制器,AMD-K7?
输入电压: 5V,12V
输出数: 1
输出电压: 1.1 V ~ 1.85 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: *
包装: 管件
HIP6004D
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004D
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Figure 10 shows the upper gate drive supplied by a direct
connection to V CC . This option should only be used in
converter systems where the main input voltage is +5V DC or
less. The peak upper gate-to-source voltage is approximately
V CC less the input supply. For +5V main power and +12V DC
for the bias, the gate-to-source voltage of Q 1 is 7V. A logic-
level MOSFET is a good choice for Q 1 and a logic-level
MOSFET can be used for Q 2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V CC .
+12V
P UPPER = Io 2 x r DS(ON) x D +
1 Io x V
2
IN x t SW x F S
+5V OR LESS
P LOWER = Io 2 x r DS(ON) x (1 - D)
V CC
-
Where: D is the duty cycle = V OUT / V IN ,
t SW is the switch ON time, and
F S is the switching frequency.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004D. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
HIP6004D
+
BOOT
UGATE
PHASE
LGATE
PGND
GND
Q 1
Q 2
NOTE:
V G-S ≈ V CC -5V
D 2
NOTE:
V G-S ≈ V CC
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V CC . The boot capacitor, C BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V CC
less the boot diode drop (V D ) when the lower MOSFET, Q 2
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
FIGURE 10. UPPER GATE DRIVE - DIRECT V CC DRIVE OPTION
Schottky Selection
Rectifier D 2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
+12V
D BOOT
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
V CC
+ V D -
+5V OR +12V
breakdown voltage must be greater than the maximum
input voltage.
BOOT
HIP6004D
UGATE
PHASE
C BOOT
Q1
NOTE:
V G-S ≈ V CC -V D
-
+
LGATE
PGND
GND
Q2
D2
NOTE:
V G-S ≈ V CC
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
11
FN4855.3
July 13, 2005
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HIP6004DCR-T 功能描述:IC CTRLR PWM VOLTAGE MON 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源,ICERA E400,E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA,WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR)
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