参数资料
| 型号： | HIP6004DCBZ |
| 厂商： | Intersil |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM VOLTAGE MON 20-SOIC |
| 标准包装： | 380 |
| 应用： | 控制器，AMD-K7? |
| 输入电压： | 5V，12V |
| 输出数： | 1 |
| 输出电压： | 1.1 V ~ 1.85 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | * |
| 包装： | 管件 |
HIP6004D
OSC
- DRIVER
- Z IN
ERROR
C O
F Z1 = ------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
F P2 = ------------------------------------
F Z2 = -------------------------------------------------------
Δ V OSC
DRIVER
PWM
COMPARATOR
+
Z FB
V E/A
+
REFERENCE
AMP
V IN
L O
PHASE
ESR
(PARASITIC)
V OUT
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1 1
2 π x R 2 x C 1 ? C 1 x C 2 ?
? C 1 + C 2 ?
1 1
2 π x ( R 1 + R 3 ) x C 3 2 π x R 3 x C 3
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
DETAILED COMPENSATION COMPONENTS
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
C 2
Z FB
Z IN
V OUT
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
C 1
COMP
-
R 2
FB
C 3
R 1
R 3
Check the compensation gain at F P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
+
compensation transfer function and plotting the gain.
HIP6004D
DACOUT
The compensation gain uses external impedance networks
F LC = -------------------------------------------
F ESR = --------------------------------------------
F Z1 F Z2
F P1
ERROR AMP GAIN
(V IN / Δ V OSC )
MODULATOR
GAIN
F LC
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The PWM wave is smoothed by the output filter (L O and C O ).
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC .
Modulator Break Frequency Equations
1 1
2 π x LO x CO 2 π x ESR x C O
The compensation network consists of the error amplifier
(internal to the HIP6004D) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 degrees . The equations below relate the compensation
network’s poles, zeros and gain to the components (R 1 , R 2 ,
R 3 , C 1 , C 2 , and C 3 ) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2 ND Zero at Filter’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
9
Z FB and Z IN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
F P2
80
OPEN LOOP
60
40
20LOG
20 (R 2 /R 1 ) 20LOG
0
COMPENSATION
-20 GAIN
CLOSED LOOP
-40 GAIN
F ESR
-60
10 100 1K 10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
FN4855.3
July 13, 2005
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6004DCBZ-T | 功能描述:电压模式 PWM 控制器 BUCK & SYNCH -RECT PWMCNTRLR & OUTPUT RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| HIP6004DCR | 功能描述:IC CTRLR PWM VOLTAGE MON 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| HIP6004DCR-T | 功能描述:IC CTRLR PWM VOLTAGE MON 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| HIP6004DCRZ | 功能描述:电压模式 PWM 控制器 BUCK & SYNCHCTIFIER PWM CNTRLR & OUTPUT RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| HIP6004DCRZ-T | 功能描述:电压模式 PWM 控制器 BUCK & SYNCHCTIFIER PWM CNTRLR & OUTPUT RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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