参数资料
型号: HIP6004ECBZ-T
厂商: Intersil
文件页数: 7/13页
文件大小: 0K
描述: IC CTRLR PWM VOLTAGE MON 20-SOIC
标准包装: 1,000
应用: 控制器,Intel VRM8.5
输入电压: 5V,12V
输出数: 1
输出电压: 1.05 V ~ 1.825 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
HIP6004E
TABLE 1. OUTPUT VOLTAGE PROGRAM (Continued)
PIN NAME
PIN NAME
VID25
NOMINAL OUTPUT
VID25
NOMINAL OUTPUT
mV
0
1
0
1
0
1
VID3
1
1
1
1
1
1
VID2
1
1
1
1
1
1
VID1
1
1
1
1
0
0
VID0
1
1
0
0
1
1
VOLTAGE DACOUT
1.300
1.325
1.350
1.375
1.400
1.425
mV
0
1
0
1
0
1
VID3
0
0
0
0
0
0
VID2
1
1
1
1
1
1
VID1
1
1
1
1
0
0
VID0
1
1
0
0
1
1
VOLTAGE DACOUT
1.700
1.725
1.750
1.775
1.800
1.825
NOTE: 0 = connected to GND or V SS , 1 = connected to V DD through pull-up resistors or leave the pins floating. Internal pull-ups will force the floating
VID pins to HIGH.
HIP6004E
V IN
BOOT
C BOOT
D 1
+V IN
Q 1
L O
V OUT
UGATE
PHASE
LGATE
PGND
Q 1
Q 2
D 2
L O
C IN
C O
V OUT
SS
C SS
HIP6004E
GND
PHASE
VCC
+12V
C VCC
Q 2
C O
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors C IN and C O each represent
numerous physical capacitors. Locate the HIP6004E within 3
inches of the MOSFETs, Q 1 and Q 2 . The circuit traces for the
MOSFETs’ gate and source connections from the HIP6004E
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, C SS
close to the SS pin because the internal current source is
only 10 μ A. Provide local V CC decoupling between VCC and
GND pins. Locate the capacitor, C BOOT as close as practical
to the BOOT and PHASE pins.
7
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V E/A ) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V IN at
the PHASE node.
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