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参数资料
| 型号： | HIP6006EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD HIP6006 |
| 应用说明： | HIP6006/07 PWM Controller ICs AppNote |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 2.5V |
| 电流 - 输出： | 9A |
| 输入电压： | 10.8 ~ 13.2 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 200kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | HIP6006 |
HIP6006
1. Pick Gain (R2/R1) for desired converter bandwidth
-
? V OSC
OSC
PWM
COMPARATOR
+
DRIVER
DRIVER
V IN
L O
PHASE
C O
V OUT
2. Place 1 ST Zero Below Filter ’s Double Pole
(~75% F LC )
3. Place 2 ND Zero at Filter ’s Double Pole
4. Place 1 ST Pole at the ESR Zero
5. Place 2 ND Pole at Half the Switching Frequency
-
Z FB
V E/A
+
ERROR
AMP
Z IN
REFERENCE
ESR
(PARASITIC)
6. Check Gain against Error Amplifier ’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter ’s
gain vs frequency. The actual Modulator Gain has a high
gain peak do to the high Q factor of the output filter and is
not shown in Figure 8. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
V OUT
Z IN
DETAILED COMPENSATION COMPONENTS
Z FB
C2
gain. Check the compensation gain at F P2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 8 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
C1
R2
C3
R3
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
COMP
R1
the gain.
HIP6006
-
+
REF
FB
100
80
60
F Z1 F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
F LC = ---------------------------------------
F ESR = ---------------------------------------------
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1 1
2 π ? L O ? C O 2 π ? ( ESR ? C O )
The compensation network consists of the error amplifier
40
20
0
-20
-40
-60
20LOG
(R2/R1)
MODULATOR
GAIN
10 100 1K
F LC
10K
20LOG
(V IN / ? V OSC )
F ESR
100K 1M 10M
COMPENSATION
GAIN
CLOSED LOOP
GAIN
(internal to the HIP6006) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 o . The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with -
20dB/decade slope and a phase margin greater than 45 o .
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
F Z1 = ----------------------------------
F P1 = -------------------------------------------------------
2 π ? R2 ? ? ---------------------- ?
F Z2 = ------------------------------------------------------
F P2 = ----------------------------------
1
2 π ? R 2 ? C1
1
2 π ? ( R1 + R3 ) ? C3
1
C1 ? C2
? C1 + C2 ?
1
2 π ? R3 ? C3
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
7
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HIP6007 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Buck Pulse-Width Modulator (PWM) Controller |
| HIP6007CB | 功能描述:IC CTRLR PWM STD BUCK 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| HIP6007CB-T | 功能描述:IC CTRLR PWM STD BUCK 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| HIP6007EVAL1 | 制造商:Intersil Corporation 功能描述:EVAL KIT FOR BUCK PULSE-WIDTH MODULATOR (PWM) CNTRLR - Bulk |
| HIP6008 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor |
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