参数资料
型号: HIP6012CV-T
厂商: Intersil
文件页数: 11/12页
文件大小: 0K
描述: IC CTRLR PWM SYNC BUCK 14-TSSOP
标准包装: 2,500
应用: 控制器,Intel Pentium? Pro、PowerP、Alpha
输入电压: 5V,12V
输出数: 1
输出电压: 1.3 V ~ 12 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
HIP6012
Small Outline Plastic Packages (SOIC)
N
M14.15 (JEDEC MS-012-AB ISSUE C)
INDEX
AREA
E
H
0.25(0.010) M
B M
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
1
2
3
L
A
A1
0.0532
0.0040
0.0688
0.0098
1.35
0.10
1.75
0.25
-
-
SEATING PLANE
B
0.013
0.020
0.33
0.51
9
-A-
D
A
h x 45 o
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
e
B
-C-
A1
μ α
0.10(0.004)
C
E
e
H
h
0.1497 0.1574
0.050 BSC
0.2284 0.2440
0.0099
0.0196
3.80 4.00
1.27 BSC
5.80 6.20
0.25
0.50
4
-
-
5
0.25(0.010) M
C A M
B S
L
0.016
0.050
0.40
1.27
6
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
N
α
0 o
14
8 o
0 o
14
8 o
7
-
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
11
Rev. 0 12/93
FN4324.2
December 27, 2004
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