参数资料
型号: HIP6013CB-T
厂商: Intersil
文件页数: 9/11页
文件大小: 0K
描述: IC CONTROLLER PWM BUCK 14-SOIC
标准包装: 2,500
应用: 控制器,Intel Pentium? Pro、PowerP、Alpha
输入电压: 5V,12V
输出数: 1
输出电压: 1.3 V ~ 12 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
HIP6013
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The HIP6013 requires an N-Channel power MOSFET. It
should be selected based upon r DS(ON) , gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
Standard-gate MOSFETs are normally recommended for
use with the HIP6013. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V CC . The boot capacitor, C BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V CC
less the boot diode drop (V D ) when the lower MOSFET, Q2
turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFET’s absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V CC .
Figure 10 shows the upper gate drive supplied by a direct
connection to VCC. This option should only be used in
converter systems where the main input voltage is +5VDC
or less. The peak upper gate-to-source voltage is
approximately V CC less the input supply. For +5V main
power and +12VDC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET is a good choice for Q1 under
these conditions.
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for the MOSFET. Switching losses also
contribute to the overall MOSFET power loss (see the
+12V
VCC
D BOOT
+5V OR +12V
equations below). These equations assume linear voltage-
current transitions and are approximations. The gate-
charge losses are dissipated by the HIP6013 and don't
heat the MOSFET. However, large gate-charge increases
HIP6013
BOOT
UGATE
PHASE
C BOOT
Q1
NOTE:
V G-S ≈ V CC - V D
the switching interval, t SW , which increases the upper
P SW = 2 I O x V IN x t SW x Fs
MOSFET switching losses. Ensure that the MOSFET is
within its maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
P COND = I O2 x r DS(ON) x D
1
Where: D is the duty cycle = V O / V IN ,
t SW is the switching interval, and
Fs is the switching frequency.
9
D2
-
+
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
4325.1
November 3, 2005
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