参数资料
型号: HIP6019BCB-T
厂商: Intersil
文件页数: 11/15页
文件大小: 0K
描述: IC REG QD BCK/LINEAR 28-SOIC
标准包装: 1,000
拓扑: 降压(降压)同步(2),线性(LDO)(2)
功能: 任何功能
输出数: 4
频率 - 开关: 215kHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 控制器
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 5 V ~ 12 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: *
包装: 带卷 (TR)
HIP6019B
compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated wave with an amplitude of
V IN at the PHASE node. The PWM wave is smoothed by
the output filter (L O and C O ).
V IN
OSC
DRIVER
2. Place 1 ST Zero below filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at filter’s Double Pole.
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at half the switching frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
F P1 = -------------------------------------------------------
F Z1 = -----------------------------------
2 π × R 2 × ? ---------------------- ?
F Z2 = -------------------------------------------------------
F P2 = -----------------------------------
? V OSC
PWM
COMP
-
+
Z FB
V E/A
-
DRIVER
Z IN
L O
PHASE
C O
ESR
(PARASITIC)
V OUT
7. Estimate Phase Margin - repeat if necessary.
Compensation Break Frequency Equations
1 1
2 π × R 2 × C1 C1 × C2
? C1 + C2 ?
1
1
2 π × ( R1 + R3 ) × C3
2 π × R 3 × C3
ERROR
AMP
+
REFERENCE
Figure 12 shows an asymptotic plot of the DC-DC
converter’s gain vs frequency. The actual modulator gain
has a peak due to the high Q factor of the output filter at F LC ,
DETAILED FEEDBACK COMPENSATION
which is not shown in Figure 12. Using the above guidelines
C2
Z FB
Z IN
V OUT
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
C1
R2
C3
R3
compensation gain. Check the compensation gain at F P2
with the capabilities of the error amplifier. The closed loop
COMP
R1
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
-
+
HIP6019B
REFERENCE
FB
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
100
F Z1 F Z2
F P1
F P2
COMPENSATION DESIGN
80
The modulator transfer function is the small-signal transfer
60
OPEN LOOP
ERROR AMP GAIN
function of V OUT /V E/A . This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at F LC and a zero at F ESR . The DC gain of the modulator is
simply the input voltage, V IN , divided by the peak-to-peak
oscillator voltage, ? V OSC .
40
20
0
-20
20LOG
(R 2 /R 1 )
MODULATOR
GAIN
20LOG
(V IN / ? V OSC )
COMPENSATION
GAIN
F LC = ----------------------------------------
F ESR = -----------------------------------------
F ESR
Modulator Break Frequency Equations
1 1
2 π × L O × C O 2 π × ESR × C O
-40
-60
10
100
1K
F LC
10K 100K
FREQUENCY (Hz)
1M
CLOSED LOOP
GAIN
10M
The compensation network consists of the error amplifier
internal to the HIP6019B and the impedance networks Z IN
and Z FB . The goal of the compensation network is to
provide a closed loop transfer function with an acceptable
0dB crossing frequency (f 0dB ) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f 0dB and 180 degrees . The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1 , R2, R3 , C1 , C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
11
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth loop. A
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Oscillator Synchronization
The PWM controllers use a triangle wave for comparison with
the error amplifier output to provide a pulse-width modulated
wave. Should the output voltages of the two PWM converters
FN4587.1
April 13, 2005
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