参数资料
型号: HIP6021CB
厂商: Intersil
文件页数: 10/15页
文件大小: 408K
描述: IC REG QD BCK/LINEAR 28-SOIC
标准包装: 26
拓扑: 降压(降压)同步(1),线性(LDO)(3)
功能: 任何功能
输出数: 4
频率 - 开关: 215kHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 控制器
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 5 V ~ 12 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: *
包装: 管件
10
OUT2 Voltage Selection
The AGP regulator output voltage is internally set to one of
two discrete levels, based on the status of the SELECT pin.
SELECT pin is internally pulled high, such that left open,
the AGP output voltage is by default set to 3.3V. The other
discrete setting available is 1.5V, which can be obtained by
grounding the SELECT pin using a jumper or another
suitable method capable of sinking a few tens of
microamperes. The status of the SELECT pin cannot be
changed during operation of the IC without immediately
causing a fault condition.
OUT3 and OUT4 Voltage Adjustability
The GTL bus voltage (1.5V, OUT3) and the chip set and/or
cache memory voltage (1.8V, OUT4) are internally set for
simple, low-cost implementation in typical Intel motherboard
architectures. However, if different voltage settings are
desired for these two outputs, the FIX pin provides the
necessary adaptability. Left open (NC), this pin sets the fixed
output voltages described above. Grounding this pin allows
both output voltages to be set by means of external resistor
dividers as shown in Figure 7.
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifiers
output of the PWM converter. This generates PHASE pulses
of increasing width that charge the output capacitor(s). After
the output voltage increases to approximately 70% of the set
value, the reference input of the error amplifier is clamped to
a voltage proportional to the SS pin voltage. The resulting
output voltages start-up as shown in Figure 3.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval and
the surge current are programmed by the soft-start capacitor,
C
SS
. Programming a faster soft-start interval increases the
peak surge current. The peak surge current occurs during the
initial output voltage rise to 70% of the set value.
Shutdown
The HIP6021 features a dedicated shutdown pin (SD). A
TTL-compatible, logic high signal applied to this pin shuts
down (disables) all four outputs and discharges the soft-start
capacitor. Following a shutdown, a logic low signal
re-enables the outputs through initiation of a new soft-start
cycle. Left open this pin will asses a logic low state, due to its
internal pull-down resistor, thus enabling normal operation of
all outputs.
The PWM output does not switch until the soft-start voltage
(V
SS
) exceeds the oscillators valley voltage. The references
on each linears error amplifier are clamped to the soft-start
voltage. Holding the SS pin low (with an open drain or
collector signal) turns off all four regulators.
The 11111 VID code also shuts down the IC.
1
1
1
1
0
2.1
1
1
1
0
1
2.2
1
1
1
0
0
2.3
1
1
0
1
1
2.4
1
1
0
1
0
2.5
1
1
0
0
1
2.6
1
1
0
0
0
2.7
1
0
1
1
1
2.8
1
0
1
1
0
2.9
1
0
1
0
1
3.0
1
0
1
0
0
3.1
1
0
0
1
1
3.2
1
0
0
1
0
3.3
1
0
0
0
1
3.4
1
0
0
0
0
3.5
NOTE: 0 = connected to GND, 1 = open or connected to 5V through
pull-up resistors
TABLE 1. OUT1 VOLTAGE PROGRAM (Continued)
PIN NAME
NOMINAL
DACOUT
VOLTAGE
VID4
VID3
VID2
VID1
VID0
DRIVE3
VSEN3
VSEN4
C
OUT4
C
OUT3
Q4
HIP6021
V
OUT3
V
OUT4
Q5
+3.3V
IN
DRIVE4
VAUX
FIX
R
S3
R
P3
R
S4
R
P4
V
OUT
V
BG
1
R
S
R
P
------- -
+
?nbsp   ?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
FIGURE 7. ADJUSTING THE OUTPUT VOLTAGE OF
OUTPUTS 3 AND 4
HIP6021
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