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参数资料
| 型号： | HIP6028EVAL1 |
| 厂商： | Intersil Corporation |
| 元件分类： | 基准电压源/电流源 |
| 英文描述： | Advanced PWM and Dual Linear Power Control with Integrated ACPI Support Interface |
| 中文描述： | 先进的双PWM和线性电源控制集成接口ACPI支持 |
| 文件页数： | 7/16页 |
| 文件大小： | 140K |
| 代理商： | HIP6028EVAL1 |
2-317
VIN2 (Pin 12)
This pin supplies power to the internal regulator. Connect
this pin to a suitable 3.3V source.
Additionally, this pin is used to monitor the 3.3V supply. If,
following a startup cycle, the voltage drops below 2.05V
(typically), the chip shuts down. A new soft-start cycle is
initiated upon return of the 3.3V supply above the under-
voltage threshold.
Description
Operation
The HIP6028 monitors and precisely controls 3 output
voltage levels (Refer to Figures 1, 2, and 3). It is designed for
microprocessor computer applications with 3.3V and 5V
power, and 12V bias input from an ATX power supply. The IC
has one PWM controller, a linear controller, and a linear
regulator. The PWM controller is designed to regulate the
microprocessor core voltage (V
OUT1
) by driving 2 MOSFETs
(Q1 and Q2) in a synchronous-rectified buck converter
configuration. The core voltage is regulated to a level
programmed by the 5-bit digital-to-analog converter (DAC).
An integrated linear regulator supplies the 2.5V clock power
(V
OUT2
). The linear controller drives an external MOSFET or
bipolar NPN (Q3) to supply the 1.5V GTL bus power
(V
OUT3
).
Initialization
The HIP6028 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12V
IN
) at the VCC pin, the 5V input voltage
(+5V
IN
) on the OCSET pin, and the 3.3V input voltage
(+3.3V
IN
) on the VIN2 pin. The normal level on OCSET is
equal to +5V
IN
less a fixed voltage drop (see over-current
protection). The POR function initiates soft-start operation
after all three input supply voltages exceed their POR
thresholds.
Soft-Start
The POR function initiates the soft-start sequence. As soon
as POR is released, the linear regulator output voltage
V
OUT2
(2.5V) quickly ramps up across the output capacitor.
The ramp dV/dt is determined by the internal 230mA current
limit and the value of the output capacitor. Simultaneously,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
11
μ
A current source charges an external capacitor (C
SS
) on
the SS pin to 4V. The PWM error amplifier reference input (+
terminal) and output (COMP pin) is clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp generates PHASE
pulses of increasing width that charge the output
capacitor(s). After this initial stage, the reference input clamp
slows the output voltage rate-of-rise and provides a smooth
transition to the final set voltage. Additionally, the linear
controller’s reference input is clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
Figure 6 shows the soft-start sequence for the typical
application. At time T0 the POR is released, SS voltage
rapidly increases to approximately 1V, and VOUT2 rapidly
ramps up to 2.5V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the 2.0V
output (VOUT1) in Figure 3, this time occurs at T2. During
the interval between T2 and T3, the error amplifier reference
ramps to the final value and the converter regulates the
output to a voltage proportional to the SS pin voltage. At T3
the input clamp voltage exceeds the reference voltage and
the output voltage is in regulation.
VOUT3 follows a ramp similar to that of the soft-start. The
PGOOD signal toggles ‘high’ when all output voltage levels
have exceeded their under-voltage levels. See the Soft-Start
Interval section under Applications Guidelines for a
procedure to determine the soft-start interval.
Fault Protection
All three outputs are monitored and protected against extreme
overload. A sustained overload on any regulator output or an
FIGURE 6. SOFT-START INTERVAL
0V
0V
0V
TIME
PGOOD
(2V/DIV)
SOFT-START
(1V/DIV)
OUTPUT
VOLTAGES
(0.5V/DIV)
V
OUT1
(DAC = 2V)
V
OUT2
AT C
OUT2
= 47
μ
F ( = 2.5V)
V
OUT3
( = 1.5V)
T1
T2
T0
POR
0V
T3
T4
HIP6028
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