参数资料
型号: HIP6301CBZ
厂商: Intersil
文件页数: 13/17页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-SOIC
标准包装: 380
PWM 型: 控制器
输出数: 1
频率 - 最大: 336kHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
HIP6301
current creates a voltage drop across R IN . This drop
increases the apparent V CORE voltage with increasing load
current, causing the system to decrease V CORE to maintain
balance at the FB pin. This is the desired “droop” voltage
Where: V CORE
V IN
L
F SW
= DC value of the output or V ID voltage
= DC value of the input or supply voltage
= value of the inductor
= switching frequency
V IN ( V CORE ) – V CORE
( L ) ( F SW ) ( V IN )
used to maintain V CORE within limits under transient
conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient.
In order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the
range when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter
components.
R IN should be selected to give the desired “droop” voltage at
the normal full load current 50 μ A applied through the R ISEN
resistor (or at a different full load current if adjusted as under
“Overcurrent, Selecting R ISEN ” above).
R IN = Vdroop/50 μ A
For a Vdroop of 80mV, R IN = 1.6k ?
The AC feedback components, R FB and Cc, are scaled in
relation to R IN .
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of all
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
r DS(ON) between synchronous rectifiers. If a FET has a
higher r DS(ON) , the current through that phase will be
reduced.
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (I LT / n),
and a sawtooth current, (i PK-PK ) resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
2
i PK – PK = -----------------------------------------------------------------
13
Example: For V CORE = 1.6V,
V IN = 12V,
L = 1.3 μ H,
F SW = 250kHz,
Then i PK-PK = 4.3A
25
20
15
10
5
0
FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING DISABLED
25
20
15
10
5
0
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING ENABLED
The inductor, or load current, flows alternately from V IN
through Q1 and from ground through Q2. The HIP6301
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, i/F SW , after Q1 is
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
average current per phase. Neglecting secondary effects,
FN4765.6
December 27, 2004
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