参数资料
型号: HIP6301EVAL2
厂商: Intersil
文件页数: 2/12页
文件大小: 0K
描述: EVALUATION BOARD HIP6301
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.6V
电流 - 输出: 54A
输入电压: 5V,12V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: HIP6301
Application Note 9906
Design Envelope
The HIP6301EVAL2 was designed to meet the performance
envelope outlined in Table 1. As such, the design covers the
full range of foreseeable upcoming Pentium 4 processors.
TABLE 1. HIP6301EVAL2 OUTPUT PARAMETERS
Figure 2 details the converter’s response to a low-frequency
55A transient. As it is evident from the scope capture, the
design implements output voltage droop as a means to meet
the dynamic transient requirements while employing a
minimum amount of output capacitance. The nominal no-
load output voltage is also offset low by design. Strict power
NO-LOAD
OUTPUT
VOLTAGE
1.685V
FULL-LOAD
OUTPUT
VOLTAGE
1.600V
MAX.
OUTPUT
CURRENT
54A
MAX. OUTPUT
CURRENT
dI/dt
400A/ μ s
requirements limit the maximum output voltage to the VID-
set voltage level (1.70V in this case).
1.7V>
HIP6301EVAL2 Performance
Output Soft-Start
The HIP6301 controller undergoes a soft-start cycle each
time power-on reset (POR) transitions from high to low (input
bias application), or when the chip is enabled for operation
VCORE
(FS/DIS pin released from a pull-down). Figure 1 details an
output soft-start cycle. Power is applied to the circuit prior to
I L2
I L4
I L3
time T0, then the circuit is disabled by shorting the FS/DIS
pin to ground. At time T0, the FS/DIS pin is released from
the short-circuit to ground, and shortly thereafter, the output
voltage starts to ramp up. The low-frequency ripple visible in
the current drawn from the input supply is a result of the
digital soft-start building the output voltage in small
0A>
T0
dI/dt = 500A/ μ s
200 μ s/DIV.
T1
increments. Similarly, this stepping method is reflected into
the output voltage and the COMP pin waveforms.
FIGURE 2. HIP6301EVAL2 OUTPUT VOLTAGE AND PHASE
CURRENTS TRANSIENT RESPONSE - LOW
FREQUENCY TRANSIENT (500Hz)
Figure 3 depicts a similar scenario, with the difference residing
in the frequency of the transient applied (33kHz). The exercise
0 V >
0A>
0A>
COMP
VCORE
I VCORE
I VCC12
is performed to detail the swift response of the converter and
the tight output voltage regulation across a typical range of
output loading. The short-duration spikes exceeding the 1.70V
maximum level would be further reduced in a practical
implementation: the processor current transient has a softer
turn on/off characteristic than the EMT test tool.
VCORE
1.7V>
PGOOD
0V>
1ms/DIV.
T0
T1
T2
FIGURE 1. HIP6301EVAL2 START-UP SEQUENCE UNDER
APPLIED CONSTANT-CURRENT OUTPUT LOAD
At time T1, the output voltage is sufficiently high to allow the
electronic load to draw the full 10A. At time T2 the soft-start
cycle ends and the PGOOD pin is enabled to report the
result of the output monitoring function.
0A>
I L2
I L4
I L3
Transient Response
Paramount to the performance of a switching regulator
dI/dt = 500A/ μ s
T0
T1
10 μ s/DIV.
T2 T3
T4
dedicated to supplying power to a microprocessor core, the
transient performance of the evaluation board has been
thoroughly documented in the following figures.
2
FIGURE 3. HIP6301EVAL2 OUTPUT VOLTAGE AND PHASE
CURRENTS TRANSIENT RESPONSE - HIGH
FREQUENCY TRANSIENT (33kHz)
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