参数资料
型号: HIP6304EVAL1
厂商: Intersil Corporation
英文描述: Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
中文描述: 微处理器核心电压调节器的多相降压PWM控制器
文件页数: 9/14页
文件大小: 176K
代理商: HIP6304EVAL1
9
Current Sensing and Balancing
Overview
The HIP6304 samples the on-state voltage drop across each
synchronous rectifier FET, Q2, as an indication of the
inductor current in that phase, see Figure 7. Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r
DS(ON)
(Q2) x inductor current (I
L
). Note that I
L
, the
inductor current, is 1/2 of the total current (I
LT
).
The voltage at Q2’s drain, the PHASE node, is applied to the
R
ISEN
resistor to develop the I
ISEN
current to the HIP6304
ISEN pin. This pin is held at virtual ground, so the current
through R
ISEN
is I
L
x r
DS(ON)
(Q2) / R
ISEN
.
The I
ISEN
current provides information to perform the
following functions:
1. Detection of an over-current condition
2. Reduce the regulator output voltage with increasing load
current (droop)
3. Balance the I
L
currents in the two phases
Over-Current, Selecting R
ISEN
The current detected through the R
ISEN
resistor is averaged
with the current detected in the other channel. The averaged
current is compared with a trimmed, internally generated
current, and used to detect an over-current condition.
The nominal current through the R
ISEN
resistor should be
50
μ
A at full output load current, and the nominal trip point for
over-current detection is 165% of that value, or 82.5
μ
A.
Therefore, R
ISEN
= I
L
x r
DS(ON)
(Q2) / 50
μ
A.
For a full load of 25A per phase, and an r
DS(ON)
(Q2) of
4m
, R
ISEN
= 2k
.
The over-current trip point would be 165% of 25A, or ~ 41A
per phase. The R
ISEN
value can be adjusted to change the
over-current trip point, but it is suggested to stay within
±
25%
of nominal.
Droop, Selection of R
IN
The average of the currents detected through the R
ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R
IN
, so the average
current creates a voltage drop across R
IN
. This drop increases
the apparent V
CORE
voltage with increasing load current,
causing the system to decrease V
CORE
to maintain balance at
the FB pin. This is the desired “droop” voltage used to maintain
V
CORE
within limits under transient conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient. In
order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the range
when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter components.
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
AVERAGING
CURRENT
SENSING
FROM
OTHER
CHANNEL
SAWTOOTH
GENERATOR
+
DIFFERENCE
R
ISEN
+
CORRECTION
ERROR
AMPLIFIER
FB
COMP
REFERENCE
DAC
TO OTHER
CHANNEL
I
SEN
R
IN
R
FB
C
c
V
CORE
Q1
Q2
COMPARATOR
REFERENCE
TO OVER
CURRENT
TRIP
L
01
PHASE
INDUCTOR
CURRENT
FROM
OTHER
CHANNEL
PWM
I
L
HIP6304
C
O
R
L
V
IN
ONLY ONE OUTPUT
STAGE SHOWN
HIP6601
-
-
-
+
-
+
-
+
HIP6304
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