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| 型号： | HIP6501ACBZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 16SOIC |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 电源电压： | 5V，12V |
| 电流 - 电源： | 20mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
HIP6501A
TABLE 2. 5V DUAL OUTPUT (V OUT3 ) TRUTH TABLE
5VSB
EN5VDL
S5
S3
5VDL
COMMENTS
0
0
1
1
1
0
5V
0V
S0, S1 STATES (Active)
S3
S3
S5
0
0
1
Note 5 Maintains Previous State
12V
0
1
1
0
1
1
0
1
0
0V
5V
5V
S4/S5
S0, S1 STATES (Active)
S3
3V3DLSB
DLA
1
0
1
Note 5 Maintains Previous State
3V3DL
1
0
0
5V
S4/S5
5VDLSB
NOTE:
5. Combination not allowed.
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5V DUAL plane supports sleep states.
TABLE 3. 2.5/3.3V MEM OUTPUT (V OUT2 ) TRUTH TABLE
5VDL
FIGURE 4. 3V DUAL AND 5V DUAL TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 1
R SEL
1k ?
1k ?
1k ?
1k ?
10k ?
10k ?
10k ?
10k ?
S5
1
1
0
0
1
1
0
0
S3
1
0
1
0
1
0
1
0
2.5/3.3V MEM
2.5V
2.5V
Note 6
0V
3.3V
3.3V
Note 6
0V
COMMENTS
S0, S1 STATES (Active)
S3
Maintains Previous State
S4/S5
S0, S1 STATES (Active)
S3
Maintains Previous State
S4/S5
5VSB
S3
S5
12V
3V3DLSB
DLA
3V3DL
NOTE:
5VDLSB
6. Combination not allowed.
5VDL
As seen in Table 3, 2.5/3.3V MEM output is maintained in S3
(Suspend-To-RAM), but not in S4/S5 state. The dual-voltage
support accommodates both SDRAM as well as RDRAM
type memories.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S4/S5) and vice versa.
Functional Timing Diagrams
Figures 4-8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of t he enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
7
FIGURE 5. 3V DUAL AND 5V DUAL TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 0
Not shown in these diagrams is the de-glitching feature used
to protect against false sleep state tripping. Once the status
of the S3 pin changes, an internal timer is activated. If at the
end of the timeout period (typically 200 μ s) the input pins
present a valid state change request, then the controller
transitions to the new configuration. Otherwise, the
previously attained valid state is maintained until valid
control signals are received from the system. This particular
feature is useful in noisy computer environments if the
control signals have to travel over significant distances.
FN4749.6
December 30, 2004
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