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参数资料
| 型号： | HIP6521EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD HIP6521 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 4，非隔离 |
| 输出电压： | 2.5V，1.5V，1.8V，2.5V |
| 电流 - 输出： | 8A，3A，3A，1A |
| 输入电压： | 3.3V，5V，12V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | HIP6521 |
Application Note 9908
they reach at time T2. Between T1 and T2, due to the fact
the ATX 3.3V output has not come up already, the 2.5VCLK
and 1.5VAGP outputs experience an under-voltage event
which keeps them off for a period of three soft-start cycles.
At time T3, the main ATX outputs start to ramp up. Time T4
signals the beginning of the 2.5VCLK and 1.5VAGP soft
starts, with the outputs reaching their set point at time T5.
Standby to Active State Transition (S3 -> S0)
Figure 4 shows the reversal of the process described in
Figure 3. By ?ipping SW2 back to the S0 (middle) position at
time T0, the ATX supply’s main outputs are enabled, along
with the HIP6521-controlled 2.5VCLK and 1.5VAGP outputs.
Time T1 signals the return of the ATX PGOOD signal back to
a high state. Noteworthy is the lack of perturbations in the
2.5VMEM and 1.8VMCH outputs during this state transition.
+5VDUAL
ATX PGOOD
+3.3VIN
2.5VMEM
2.5VCLK
2.5VMEM
+3.3VIN
1.8VMCH
1.5VAGP
1.8VMCH
1.5VAGP
GND >
5ms/DIV.
GND >
T0
T1
T2
T3
T4
T5
2.5VCLK
100ms/DIV.
FIGURE 2. HIP6521EVAL1 START-UP
T0
T1
Active to Standby State Transition (S0 -> S3)
Figure 3 shows a typical active (S0) to S3 standby state
transition. Prior to time T0, the HIP6521EVAL1 was
operating in active state. At time T0, SW2 is switched into
the ‘S3’ position. As a result, the main ATX outputs, as well
as the 2.5VCLK and 1.5VAGP outputs are shut down. Even
though the ATX is effectively shut down at time T0, the ATX
PGOOD output signals the fact that the main outputs will go
out of regulation only at time T1. At time T2, the ATX 3.3V
outputs start to discharge, falling out of regulation.
Throughout the transition, the 2.5VMEM and 1.8VMCH
outputs rigorously maintain their regulation.
ATX PGOOD
+3.3VIN
FIGURE 4. S3 STANDBY TO ACTIVE STATE TRANSITION
Due to the similar transition response, only S3 state
transitions are detailed.
Transient Response
Figure 5 details the transient response of all four outputs
controlled by the HIP6521 under the effect of concurrent
loading. The characteristics of the loads the outputs were
subject to during this test are listed in Table 2. To summarize
the information, all outputs were transiently loaded with 10%
to 100% of their maximum output rating, under nominal
current rate of change, a 40% duty cycle, and different
frequencies resulting in random load overlapping. The test
was designed to stress the application in a manner
representative of a worst-case situation. Even under such
loading, the HIP6521EVAL1 exhibits exemplary response
and crosstalk immunity, both characteristics easily noticed in
Figure 5.
TABLE 2. OUTPUT TRANSIENT LOADING DESCRIPTION
2.5VMEM
OUTPUT
I OUT(MIN)
(A)
I OUT(MAX)
(A)
dI OUT /dt
(A/ μ s )
Frequency
(Hz)
1.5VAGP
1.8VMCH
2.5VMEM
2.5VCLK
0.8
0.1
8.0
1.0
1.0
0.1
1000
800
GND >
2.5VCLK
100ms/DIV.
1.8VMCH
1.5VAGP
0.3
0.3
3.0
3.0
1.0
1.0
650
1500
T0
T1
T2
NOTE: All transients applied had a 40% duty cycle.
FIGURE 3. ACTIVE TO S3 STANDBY STATE TRANSITION
3
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