- 您现在的位置：买卖IC网 > PDF目录370643 > HMP8112 (Harris Corporation) NTSC/PAL Video Decoder PDF资料下载
参数资料
| 型号： | HMP8112 |
| 厂商： | Harris Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL视频解码器 |
| 文件页数： | 18/40页 |
| 文件大小： | 563K |
| 代理商： | HMP8112 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
18
TABLE 20. HORIZONTAL SYNC END TIME REGISTER
DESTINATION ADDRESS = 0E
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Horizontal Drive
Programmable End
Time
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
0010 0000
B
TABLE 21. HORIZONTAL SYNC END TIME REGISTER
DESTINATION ADDRESS = 0F
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
XXXX XX
9 - 8
Horizontal Drive
Programmable End
Time
This register provides a programmable delay for the external HDRIVE signal. The end
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
00
B
TABLE 22. PHASE LOCKED LOOP ADJUST REGISTER
DESTINATION ADDRESS = 10
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Phase Locked Loop
Filter Adjust Test
Register
The Phase Locked Loop time constants can be changed for testing purposes. It is rec-
ommended that the default value of (20
H
) always be used. The reset state is 00
H
.
0000 0000
B
TABLE 23. PHASE LOCKED LOOP SYNC DETECT WINDOW REGISTER
DESTINATION ADDRESS = 11
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Phase Locked Loop
Horizontal Sync
Detect Window
These bits control the PLL horizontal sync detect window. This window sets the length
of time that the line lock PLL will allow the detection of the HSYNC. HSYNC outside of
this window are declared missing and will cause the missing sync logic to start counting
missing syncs. For NTSC this value should be DD
H
and for PAL, FF
H
.
1101 1101
B
TABLE 24. DC RESTORE START TIME REGISTER
DESTINATION ADDRESS = 12
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
DC Restore
Programmable Start
Time
This register provides a programmable delay for the internal DC RES signal. The start
time of the DC RES pulse is set from the detection of horizontal sync in the video data.
DC RES is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This signal is used to run the GATE B pin of the A/D con-
verter. This is the lower byte of the 10-bit word.
0011 0111
B
HMP8112
相关PDF资料 |
PDF描述 |
|---|---|
| HMP8112ACN | NTSC/PAL Video Decoder |
| HMP8112CN | NTSC/PAL Video Decoder |
| HMP8112EVAL2 | NTSC/PAL Video Decoder |
| HMP8156EVAL2 | NTSC/PAL Video Decoder |
| HMP8156EVAL1 | NTSC/PAL Encoders |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HMP8112/8115 WAF | 制造商:Harris Corporation 功能描述: |
| HMP8112ACN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8112CN | 制造商:HARRIS 制造商全称:HARRIS 功能描述:NTSC/PAL Video Decoder |
| HMP8112EVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8112EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。