参数资料
| 型号： | HMP8117CNZ |
| 厂商： | Intersil |
| 文件页数： | 2/45页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO DECODER NTSC/PAL 80PQFP |
| 标准包装： | 66 |
| 类型： | 视频解码器 |
| 应用： | 视频 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-BQFP |
| 供应商设备封装： | 80-QFP（14x20） |
| 包装： | 托盘 |
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10
FN4643.4
July 29, 2009
BLANK and DVALID Timing
DVALID is asserted when P15-P0 contain valid data. The
behavior of the DVALID output is determined by bit 4
(DVLD_LTC) and bit 5 (DLVD_DCYC) of the GENLOCK
CONTROL register 04H for each video output mode.
The BLANK output pin is used to distinguish the blanking
interval period from active video data. The blanking intervals
are programmable in both horizontal and vertical
dimensions. Reference Figure 7 for active video timing and
use Table 3 for typical blanking programming values.
During active scan lines, BLANK is asserted when the
horizontal pixel count matches the value in the START
H_BLANK register 31H/30H. The pixel counter is 000H at the
leading edge of the sync tip after a fixed pipeline delay.
Since blanking normally occurs on the front porch, (prior to
count 000H) the START H_BLANK count must be
programmed with a large value from the previous line. Refer
to the Last Pixel Count from Table 3. BLANK is negated
when the horizontal pixel count matches the value in the
END H_BLANK register 32H. Note that horizontally, BLANK
is programmable with two pixel resolution.
START V_BLANK register 34H/33H and END V_BLANK
register 35H determine which scan lines are blanked for each
field. During inactive scan lines, BLANK is asserted during the
entire scan line. Half-line blanking of the output video cannot
be done.
FIGURE 4. NTSC(M) AND PAL(M) EVEN FIELD TIMING
VIDEO
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
HSYNC
INPUT
261
PAL(M) LINE#
262
263
264
265
266
267
268
269
270
260
259
264
NTSC(M) LINE#
265
266
267
268
269
270
271
272
273
263
262
VIDEO
VSYNC
FIELD
‘EVEN’ FIELD
FIGURE 5. PAL(B, D, G, H, I, N, NC) ODD FIELD TIMING
‘ODD’ FIELD
HSYNC
INPUT
623
LINE #
624
625
1234567
622
621
FIGURE 6. PAL(B, D, G, H, I, N, NC) EVEN FIELD TIMING
VIDEO
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
HSYNC
INPUT
311
LINE #
312
313
314
315
316
317
318
319
320
310
309
HMP8117
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