参数资料
型号: HUF76629D3ST
厂商: Fairchild Semiconductor
文件页数: 2/10页
文件大小: 0K
描述: MOSFET N-CH 100V 20A DPAK
产品培训模块: High Voltage Switches for Power Processing
标准包装: 2,500
系列: UltraFET™
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 100V
电流 - 连续漏极(Id) @ 25° C: 20A
开态Rds(最大)@ Id, Vgs @ 25° C: 52 毫欧 @ 20A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 46nC @ 10V
输入电容 (Ciss) @ Vds: 1285pF @ 25V
功率 - 最大: 110W
安装类型: 表面贴装
封装/外壳: TO-252-3,DPak(2 引线+接片),SC-63
供应商设备封装: D-Pak
包装: 带卷 (TR)
HUF76629D3S
Electrical Specifications
T C = 25 o C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BV DSS
I DSS
I GSS
I D = 250 μ A, V GS = 0V (Figure 12)
I D = 250 μ A, V GS = 0V , T C = -40 o C (Figure 12)
V DS = 95V, V GS = 0V
V DS = 90V, V GS = 0V, T C = 150 o C
V GS = ± 16V
100
90
-
-
-
-
-
-
-
-
-
-
1
250
± 100
V
V
μ A
μ A
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
V GS(TH)
r DS(ON)
V GS = V DS , I D = 250 μ A (Figure 11)
I D = 20A, V GS = 10V (Figures 9, 10)
I D = 20A, V GS = 5V (Figure 9)
I D = 20A, V GS = 4.5V (Figure 9)
1
-
-
-
-
0.0415
0.046
0.047
3
0.052
0.054
0.055
V
?
?
?
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
R θ JC
R θ JA
TO-252AA
-
-
-
-
1.36
100
o C/W
o C/W
Ambient
SWITCHING SPECIFICATIONS (V GS = 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t ON
t d(ON)
t r
t d(OFF)
t f
t OFF
V DD = 50V, I D = 20A
V GS = 4.5V, R GS = 6.8 ?
(Figures 15, 21, 22)
-
-
-
-
-
-
-
11
114
38
60
-
190
-
-
-
-
145
ns
ns
ns
ns
ns
ns
SWITCHING SPECIFICATIONS (V GS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t ON
t d(ON)
t r
t d(OFF)
t f
t OFF
V DD = 50V, I D = 20A
V GS = 10V,R GS = 8.2 ?
(Figures 16, 21, 22)
-
-
-
-
-
-
-
6.8
28
67
60
-
50
-
-
-
-
190
ns
ns
ns
ns
ns
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain "Miller" Charge
Q g(TOT)
Q g(5)
Q g(TH)
Q gs
Q gd
V GS = 0V to 10V
V GS = 0V to 5V
V GS = 0V to 1V
V DD = 50V,
I D = 20A,
I g(REF) = 1.0mA
(Figures 14, 19, 20)
-
-
-
-
-
38
21
1.2
3.3
10
46
25
1.6
-
-
nC
nC
nC
nC
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C ISS
C OSS
C RSS
V DS = 25V, V GS = 0V,
f = 1MHz
(Figure 13)
-
-
-
1285
270
65
-
-
-
pF
pF
pF
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
V SD
t rr
Q RR
TEST CONDITIONS
I SD = 20A
I SD = 10A
I SD = 20A, dI SD /dt = 100A/ μ s
I SD = 20A, dI SD /dt = 100A/ μ s
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.00
110
370
UNITS
V
V
ns
nC
?2001 Fairchild Semiconductor Corporation
HUF76629D3S Rev. C0
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