参数资料
型号: HW-AFX-FF1760-500-G
厂商: Xilinx Inc
文件页数: 11/26页
文件大小: 0K
描述: BOARD DEV VIRTEX 5 FF1760
标准包装: 1
系列: Virtex®-5 LX
类型: FPGA
适用于相关产品: Virtex?-5 LX FF1760
所含物品: 板,线缆,连接器,振荡器,真空处理工具
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Detailed Description
Table 1:
Voltage Ranges
Label
VCCINT
VCCO
VCCAUX
VCC1V8
Maximum Voltage
1.0V
2.5V
2.5V
1.8V
Maximum Current
7A
4A
3A
3A
Off Position
In the OFF position, the power switch disables all modes of powering the DUT.
Power Enable Jumpers
For each power supply there are headers (J20, J19, and J21) marked REG ENABLE or
REG|JACK. Placement of jumpers on these headers enables delivery of all power from the
onboard regulators. Removing all jumpers allows the user to provide power from the three
power supply jacks marked VCCINT (J33), VCCO (J31), and VCCAUX (J30).
Note: If using an external bench top power supply, 5V must be applied to the 5V jack, J32, for proper
operation.
2. Power Supply Jacks
One method of delivering power to the DUT is by way of the power supply jacks: VCCINT
(J33), VCCO (J31), and VCCAUX (J30). (Consult the Virtex-5 FPGA Data Sheet: DC and
Switching Characteristics [Ref 1] for the maximum voltage rating for each device.) The
power supply jacks are:
?
VCCINT
?
Supplies voltage to the V CCINT of the DUT
?
VCCO
?
?
Supplies I/O voltages to the DUT
Each bank can be powered from one of two sources (V CCO , V CCINT ) by
appropriate placement of jumpers on the header
?
VCCAUX
?
Supplies voltage to the V CCAUX DUT pins
Virtex-5 LX FPGA Prototype Platform
UG222 (v1.1.1) March 21, 2011
11
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