参数资料
型号: HW-AFX-FF1760-500-G
厂商: Xilinx Inc
文件页数: 13/26页
文件大小: 0K
描述: BOARD DEV VIRTEX 5 FF1760
标准包装: 1
系列: Virtex®-5 LX
类型: FPGA
适用于相关产品: Virtex?-5 LX FF1760
所含物品: 板,线缆,连接器,振荡器,真空处理工具
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Detailed Description
4. JTAG Chain
J41 is a 2 x 3 header ( Figure 3 ) that allows users to select either the ISPROM or the FPGA or
both devices in the JTAG chain. Table 4 shows the jumper settings for the JTAG chain
header.
X-Ref Target - Figure 3
J41
PROM_TDO
TDI
1
3
5
2
4
6
FPGA_TDO
ON_BOARD_TDO
UG222_03_051506
Figure 3:
JTAG Chain Jumper
Table 4:
J41 Jumper Settings
J41 Pin Jumpers
PROM JTAG
FPGA JTAG
1-3
3-5
2-4
4-6
Enable
Disable
Enable
Disable
5. JTAG Termination Header
When connecting another board to the downstream System ACE interface connector (P3)
or the downstream interface connector (P4), jumper pins 1-2 on the JTAG termination
header (J22); otherwise jumper pins 2-3 for on-board termination.
The TCK and TMS pins are parallel feedthrough connections from the upstream
System ACE interface connector to the downstream System ACE interface connector and
drive the TCK and TMS pins of the onboard PROM and the DUT.
Note: The termination jumper must be in place on the last board in the chain to connect the TDO pin
of the final device to the TDO feedback chain.
Virtex-5 LX FPGA Prototype Platform
UG222 (v1.1.1) March 21, 2011
13
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