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参数资料
| 型号： | HW-RIBBON14 |
| 厂商： | Xilinx Inc |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | CABLE FOR CABLE IV OR MULTIPRO |
| 标准包装： | 1 |
| 附件类型： | 14 引脚带状线缆 |
| 适用于相关产品： | 并行线缆 IV 和 MultiPRO |
| 产品目录页面： | 600 (CN2011-ZH PDF) |
| 其它名称： | 122-1476 |
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Pinout Assignments
Table 2: PC4 Target Interface Connector Signal Assignments
Xilinx Parallel Cable IV
JTAG
Pin Name (1)
Slave
Serial
SPI
Type
Flying
Lead
Wires
Ribbon
Cable
Description
Test Data In . This is the target serial input data stream for JTAG
TDI
–
–
Out
2
10
operations and should be connected to the TDI pin on the first ISP
device in the JTAG chain.
Test Data Out . This is the target serial output data stream for
TDO
–
–
In
3
8
JTAG operations and should be connected to the TDO pin on the
last ISP device in the JTAG chain.
Test Clock . This is the clock signal for JTAG operations and
TCK
–
–
Out
5
6
should be connected to the TCK pin on all target ISP devices that
share the same data stream.
Test Mode Select . This is the JTAG mode signal that establishes
TMS
–
–
Out
1
4
appropriate TAP state transitions for target ISP devices. It should
be connected to the TMS pin on all target ISP devices that share
the same data stream.
Configuration Initialize . This pin indicates that configuration
–
INIT
–
In/Out
4
14
memory is being cleared. It should be connected to the INIT_B pin
of the target FPGA in a single device system or to the INIT_B pin
on all FPGAs in daisy-chained configurations.
Configuration Data Input . This is the serial input data stream for
–
DIN
–
Out
2
10
target FPGA(s). It should be connected to the DIN pin of the target
FPGA in a single device system or to the DIN pin of the first FPGA
in daisy-chained configurations.
Configuration Done . This pin indicates to PC4 that the target
FPGA(s) have received the entire configuration bit stream. It
–
DONE
–
In
3
8
should be connected to the DONE pin on all FPGAs for daisy-
chained configurations. Additional CCLK cycles are issued
following the positive transition of DONE to ensure that the
configuration process is complete.
Configuration Clock . In slave-serial configuration mode, FPGAs
are configured by loading one bit per CCLK cycle. CCLK should be
–
CCLK
–
Out
5
6
connected to the CCLK pin on the target FPGA for a single device
system or to the CCLK pin of all FPGAs in daisy-chained
configurations.
Configuration Reset . This pin is used to force a reconfiguration of
–
PROG
–
Out
1
4
the target FPGA(s). It should be connected to the PROG_B pin of
the target FPGA in a single device system or to the PROG_B pin
of all FPGAs in daisy-chained configurations.
SPI Master-Output Slave-Input. This pin is the target serial input
–
–
MOSI
Out
2
10
data stream for SPI operations and should be connected to the D (2)
pin on the SPI flash PROM.
SPI Master-Input, Slave-Output. This pin is the target serial
–
–
MISO
In
3
8
output data stream for SPI operations and should be connected to
the Q (2) pin on the SPI flash PROM.
–
–
V TST
–
–
V TST
SCK
SS
V TST
Out
Out
Out
5
1
6
4
12
SPI Clock. This pin is the clock signal for SPI operations and
should be connected to the C (2) pin on the SPI flash PROM.
SPI Select. This pin is the active-Low SPI chip select signal. This
should be connected to the S (2) pin on the SPI flash PROM.
Test Driver . This pin is reserved for Xilinx diagnostics and should
not be connected to any target circuitry.
Target Reference Voltage . This pin should be connected to a
voltage bus on the target system that supplies the SPI, JTAG or
V REF
V REF
V REF
In
7
2
slave serial interface. For example, when communicating with
CoolRunner II device using the JTAG interface, V REF should be
connected to the target V AUX bus. V REF must be connected to a
regulated voltage. There must not be any current limiting resistor.
DS097 (v2.5) May 14, 2008
Product Specification
4
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