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参数资料
| 型号： | HW-RIBBON14 |
| 厂商： | Xilinx Inc |
| 文件页数： | 8/9页 |
| 文件大小： | 0K |
| 描述： | CABLE FOR CABLE IV OR MULTIPRO |
| 标准包装： | 1 |
| 附件类型： | 14 引脚带状线缆 |
| 适用于相关产品： | 并行线缆 IV 和 MultiPRO |
| 产品目录页面： | 600 (CN2011-ZH PDF) |
| 其它名称： | 122-1476 |
R
Status LED
The Status LED indicates one of two possible conditions as
shown in the following table.
Xilinx Parallel Cable IV
A sensing circuit continuously monitors the V REF pin. If
V REF drops below 1.3V DC, all output buffers are 3-stated to
avoid any possible damage when connected to a non-
powered target system.
LED State
Solid Green
Operating Condition
Power available to POD and V REF detected.
All pins are protected against continuous shorts to ground
or voltages up to 5.5V DC.
Solid Amber Power available to POD but no V REF detected.
Notes:
1. If LED does not turn on, check to make sure that power has been
connected to the PC4 either through the mouse/keyboard port or
through the external power connector.
Automatic I/O Voltage Sensing
Although JTAG configuration pins have typically operated at
3.3V or 5.0V, new devices support voltages as low as 1.5V.
Voltage levels for Slave-Serial configuration pins follow the
respective I/O bank voltage, which can be in the range from
1.5V to 5.0V. SPI pin voltage levels are the same as the SPI
device power supply voltage which is typically 3.3V or 2.5V.
Consequently, the PC4 output buffers must be capable of
driving at the voltage level expected by the receiving
devices. The V REF pin on the target device is used to bias
the PC4 output buffers.
PC4 Operating Characteristics
Absolute Maximum Ratings
IEEE 1284 Cable Specifications
Level 1 compliant host ports are designed to operate over a
maximum cable length of 10 ft. Level 2 compliant host ports
operates over a maximum cable length of 33 ft. PC4 uses a
Level 2 compliant cable interface buffer.
For more cable information, see the following web site:
Signal Integrity Issues
The PC4 uses high slew rate buffers to drive TCK, TMS, and
TDI. Users should pay close attention to proper PCB layout
and signal termination to avoid transmission line effects.
Users are encouraged to refer to the Xilinx "Signal Integrity "
documentation and the application note XAPP361 , Planning
for High Speed XC9500XV Designs , on the Xilinx web site.
Symbol
V CC
T A
T STG
P D
I OUT
Description
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
DC Output Current (TDI, TCK, TMS, INIT)
Value
5.5
0? to +70?
–40? to +85?
750
±32
Units
V
C
C
mW
mA
Recommended Operating Conditions
Symbol
V CC
V REF
I CC
I REF
V OH
V OL
V IH
V IL
Parameter
DC Supply Voltage
Target Reference Voltage
Operating Current
Reference Current
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
Conditions
External P/S
V REF = 3.3V DC, I OH = –4 mA
V REF = 3.3V DC, I OL = +4 mA
V REF > 1.5V
V REF > 1.5V
Min
4.75
1.5
60
6.0
2.7
–
1.2
–
Max
5.25
5.5
100
15.0
–
0.36
–
0.4
Units
V
V
mA
mA
V
V
V
V
Ordering Information
The device number is HW-PC4.
DS097 (v2.5) May 14, 2008
Product Specification
8
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