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参数资料
| 型号： | HW-V4-ML405-UNI-G-J |
| 厂商： | Xilinx Inc |
| 文件页数： | 21/35页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM VIRTEX-4 |
| 标准包装： | 1 |
| 系列： | Virtex®-4 |
| 类型： | FPGA |
| 适用于相关产品： | XC4VFX20-FF672 |
| 所含物品： | 评估平台，小型闪存卡，DDR2 DImm，LCD 显示器 - 不包括电源 - |
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Detailed Description
11. Stereo AC97 Audio Codec
The ML405 evaluation platform has an AC97 audio codec (U14) to permit audio
processing. The National Semiconductor LM4550 Audio Codec supports stereo 16-bit
audio with up to 48-kHz sampling. The sampling rate for record and playback can be
different.
Note: The reset for the AC97 codec is shared with the reset signal for the flash memory chips and
is asserted at power-on or upon system reset.
Separate audio jacks are provided for Microphone, Line In, Line Out, and Headphone. All
jacks are stereo except for Microphone. The Headphone jack is driven by the audio codec's
internal 50-mW amplifier. Table 1-11 summarizes the audio jacks.
Table 1-11:
Reference
ML405 Audio Jacks
Description
Designator
J11
J12
J13
J14
Function
Microphone - In
Analog Line - In
Analog Line - Out
Headphone - Out
Stereo/Mono
Mono
Stereo
Stereo
Stereo
12. RS-2 3 2 Serial Port
The ML405 board contains one male DB-9 RS-232 serial port, allowing the FPGA to
communicate serial data with another device. The serial port is wired as a host (DCE)
device. Therefore, a null modem cable is normally required to connect the board to the
serial port on a PC. The serial port is designed to operate up to 115200 Bd. An interface chip
is used to shift the voltage level between FPGA and RS-232 signals.
Note: The FPGA is connected only to the TX and RX data pins on the serial port. Therefore, other
RS-2 3 2 signals, including hardware flow-control signals, are not used. Flow control should be
disabled when communicating with a PC.
A secondary serial interface is available by using header J27 to support debug of the USB
controller chip. Header J27 brings out RS-232 voltage level signals for ground, TX data, and
RX data.
1 3 . 16-Character x 2-Line LCD
The ML405 board has a 16-character x 2-line LCD (Lumex LCM-S01602DTR/M) on the
board to display text information. Potentiometer R1 adjusts the contrast of the LCD. The
data interface to the LCD is connected to the FPGA to support 4-bit mode only. A level
translator chip is used to shift the voltage level between the FPGA and the LCD.
Note: Care should be taken not to scratch or damage the surface of the LCD window.
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
21
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| HW-V4-ML410-UNI-G-J | 功能描述:EVALUATION PLATFORM VIRTEX-4 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-4 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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