参数资料
型号: HY29LV320TF-80
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 32 Mbit (2M x 16) Low Voltage Flash Memory
中文描述: 2M X 16 FLASH 3V PROM, 80 ns, PBGA63
封装: 7 X 11 MM, FBGA-63
文件页数: 26/44页
文件大小: 323K
代理商: HY29LV320TF-80
26
r1.3/May 02
HY29LV320
START
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data
NO
YES
PROGRAM/ERASE
COMPLETE
DQ[5] = 1
NO
YES
Test for DQ[7] = 1
for Erase Operation
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data
(Note 2)
NO
YES
Test for DQ[7] = 1
for Erase Operation
PROGRAM/ERASE
EXCEEDED TIME ERROR
Notes:
1. During
programming
, the program address. During
sector erase
, an
address within any non-protected sector specified for erasure. During
chip erase
, an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously to DQ[5].
Figure 9. Data# Polling Test Algorithm
DQ[2] toggles when the host reads at addresses
within sectors that have been specified for era-
sure, but cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ[6],
by comparison, indicates whether the device is ac-
tively erasing or is in Erase Suspend, but cannot
distinguish which sectors are specified for erasure.
Thus, both status bits are required for sector and
mode information.
Figure 10 illustrates the operation of Toggle Bits I
and II.
DQ[5] - Exceeded Timing Limits
DQ[5] is set to a
1
when the program or erase
time has exceeded a specified internal pulse count
limit. This is a failure condition that indicates that
the program or erase cycle was not successfully
completed. DQ[5] status is valid only while DQ[7]
or DQ[6] indicate that the Automatic Algorithm is
in progress.
The DQ[5] failure condition will also be signaled if
the host tries to program a
1
to a location that is
previously programmed to
0
, since only an erase
operation can change a
0
to a
1
.
For both of these conditions, the host must issue
a Reset command to return the device to the Read
mode.
Note:
While DQ[5] indicates an error condition, no com-
mands (except Reads) will be accepted by the device. If
the device receives a command while DQ[5] is high, the
first write cycle of that command will reset the error con-
dition and the remaining write cycles of that command
sequence will be ignored
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a
0
to a
1
. Refer to the
Sector Erase Command
section for additional information. Note that the
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a
1
,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a
0
, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
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