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参数资料
| 型号： | HY29LV320TT-90 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 32 Mbit (2M x 16) Low Voltage Flash Memory |
| 中文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封装： | TSOP-48 |
| 文件页数： | 15/44页 |
| 文件大小： | 323K |
| 代理商： | HY29LV320TT-90 |
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15
r1.3/May 02
HY29LV320
ing specific data items listed in Table 5.
The Elec-
tronic ID data can also be obtained by the host
through specific commands issued via the com-
mand register, as described later in the
‘
Device
Commands
’
section of this data sheet.
While in the high-voltage Electronic ID mode, the
system may read at specific addresses to obtain
certain device identification and status informa-
tion:
A read cycle at address 0xXXX00 retrieves the
manufacturer code.
A read cycle at address 0xXXX01 returns the
device code.
A read cycle containing a sector address (SA)
in A[20:12] and the address 0x04 in A[7:0] re-
turns 0x01 if that sector is protected, or 0x00 if
it is unprotected.
A read cycle at address 0xXXX03 returns 0x80
if the Sec
2
region is protected and locked at
the factory and 0x00 if it is not.
DEVICE COMMANDS
Figure 5. Temporary Sector Unprotect
Algorithm
START
RESET# = V
(All protected sectors
become unprotected)
Perform Program or Erase
Operations
RESET# = V
(All previously protected
sectors return to protected
state)
TEMPORARY SECTOR
UNPROTECT COMPLETE
Device operations are initiated by writing desig-
nated address and data
command sequences
into
the device. Commands are routed to the com-
mand register for execution. This register is auto-
matically selected as the destination for all write
operations and does not need to be explicitly ad-
dressed. Addresses are latched on the falling
edge of WE# or CE#, whichever happens later.
Data is latched on the rising edge of WE# or CE#,
whichever happens first.
A command sequence is composed of one, two
or three of the following sub-segments: an
unlock
cycle
, a
command cycle
and a
data cycle
. Table
8 summarizes the composition of the valid com-
mand sequences implemented in the HY29LV320,
and these sequences are fully described in Table
9 and in the sections that follow.
Writing incorrect address and data values or writ-
ing them in the improper sequence resets the de-
vice to the Read mode.
Reading Data
The device automatically enters the read array
mode after device power-up, after the RESET#
input is asserted and upon the completion of cer-
tain commands. Commands are not required to
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Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
4. Any number of CFI data read cycles are permitted.
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Table 8. Composition of Command Sequences
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| HY29LV320BT-90 | 32 Mbit (2M x 16) Low Voltage Flash Memory |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY29LV320TT-90I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:32 Mbit (2M x 16) Low Voltage Flash Memory |
| HY29LV400 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4M(X8/X16)|3.0V|55|NOR FLASH - 4M |
| HY29LV400BF55 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory |
| HY29LV400BF55I | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory |
| HY29LV400BF70 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory |
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