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参数资料
| 型号： | HY51V64403HG(HGL) |
| 英文描述： | 16Mx4|3.3V|8K|45|FP/EDO DRAM - 64M |
| 中文描述： | 16Mx4 | 3.3 | 8K的| 45 |计划生育/ EDO公司的DRAM - 6400 |
| 文件页数： | 6/12页 |
| 文件大小： | 104K |
| 代理商： | HY51V64403HG(HGL) |
HY51V(S)16160HG/HGL
Rev.0.1/Apr.01
6
CAPACITANCE
(Vcc=3.3V +/-10%, TA=25
°
C
)
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /UCAS and /LCAS = V
IH
to disable D
out
AC CHARACTERISTICS
(Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18, 19)
Read, Write, Read-modify-Write and Refresh Cycle
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (Address)
CI1
-
5
pF
1
Input capacitance (Clocks)
CI2
-
5
pF
1
Output capacitance (Data-in, Data-out)
CI/O
-
7
pF
1, 2
Parameter
Symbol
-50
-60
-70
Unit
Note
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
-
110
-
130
-
ns
/RAS precharge time
t
RP
30
-
40
-
50
-
ns
/CAS precharge time
t
CP
8
-
10
-
10
-
ns
24
/RAS pulse width
t
RAS
50
10,000
60
10,000
70
10,000
ns
/CAS pulse width
t
CAS
13
10,000
15
10,000
18
10,000
ns
Row address set-up time
t
ASR
0
-
0
-
0
-
ns
Row address hold time
t
RAH
8
-
10
-
10
-
ns
Column address set-up time
t
ASC
0
-
0
-
0
-
ns
21
Column address hold time
t
CAH
8
-
10
-
15
-
ns
21
/RAS to /CAS delay time
t
RCD
18
45
20
45
20
52
ns
3
/RAS to Column address delay time
t
RAD
13
30
15
30
15
35
ns
4
/RAS hold time
t
RSH
13
-
15
-
18
-
ns
/CAS hold time
t
CSH
50
-
60
-
70
-
ns
23
/CAS to /RAS precharge time
t
CRP
5
-
5
-
5
-
ns
22
Test Condition
Input rise and fall times = 5ns
Input timing reference level : V
IL
/V
IH
= 0.8/2.0V
Output timing reference level :
V
OL
/V
OH
=0.8/0.2V
Output load : 1 TTL gate + C
L
(100pF)
( including scope and jig )
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