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参数资料
| 型号： | HY51V65803HG(HGL) |
| 英文描述： | 8Mx8|3.3V|4K|45|FP/EDO DRAM - 64M |
| 中文描述： | 8Mx8 | 3.3 | 4K的| 45 |计划生育/ EDO公司的DRAM - 6400 |
| 文件页数： | 10/12页 |
| 文件大小： | 104K |
| 代理商： | HY51V65803HG(HGL) |
HY51V(S)16160HG/HGL
Rev.0.1/Apr.01
10
Notes :
1. AC measurements assume t
T
= 5ns
2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles
( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh)
3. Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is specified as a
reference point only : if t
RCD
is greater than the specified t
RCD
(max) limit, then access time is
controlled exclusively by t
CAC
.
4. Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is specified as a
reference point only : if t
RAD
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. Either t
ODD
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals, also transition times
are measured between V
IH
(min) and V
IL
(max)
8. Assumes that t
RCD
<=t
RCD
(max) and t
RAD
<=t
RAD
(max). If t
RCD
or t
RAD
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown
9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.( V
OH
=2.0V, V
OL
=0.8V)
10. Assumes that t
RCD
>=t
RCD
(max) and t
RCD
+ t
CAC
(max) >= t
RAD
+ t
AA
(max)
11. Assumes that t
RAD
>=t
RAD
(max) and t
RCD
+ t
CAC
(max) <= t
RAD
+ t
AA
(max)
12. Either t
RCH
of t
RRH
must be satified for a read cycles
13. t
OFF
(max), t
OEZ
(max), t
OFR
(max) and t
WEZ
(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels
14. t
WCS
, t
RWD
, t
CWD
, t
AWD
and t
CPW
are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only : If t
WCS
>=t
WCS
(min), the cycle is an early write
cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle :
If t
RWD
>=t
RWD
(min), t
CWD
>=t
CWD
(min), t
AWD
>=t
AWD
(min), the cycle is a read-modify-write and
the data output will contain data read from the selected cell : if neither of the above sets of conditions
is satified, the condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to /UCAS and /LCAS leading edge in early write cycles and to /WE
leading edge in delayed write or read-modify-write cycles
16. t
RASP
defines /RAS pulse width in Fast p
age mode cycles
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