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参数资料
| 型号： | HY57V2578020LTC-10S |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封装： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件页数： | 1/11页 |
| 文件大小： | 126K |
| 代理商： | HY57V2578020LTC-10S |
HY57V2578020
4Banks x 8M x 8Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Revision 0.1 / Jul.98
DESCRIPTION
The Hyundai HY57V2578020 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory
applications which require large memory density and high bandwidth. HY57V2578020 is organized as 4banks of
8,388,608x8.
HY57V2578020 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
Single 3.3V
± 0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V2578020TC-8
125MHz
Normal
4Banks x 8Mbits
x8
LVTTL
400mil 54pin TSOP II
HY57V2578020TC-10P
100MHz
HY57V2578020TC-10S
100MHz
HY57V2578020TC-10
100MHz
HY57V2578020LTC-8
125MHz
Low Power
HY57V2578020LTC-10P
100MHz
HY57V2578020LTC-10S
100MHz
HY57V2578020LTC-10
100MHz
Preliminary
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY57V281620A | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ALT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8Mx16|3.3V|4K|6|SDR SDRAM - 128M |
| HY57V281620ALT-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x16 SDRAM |
| HY57V281620ALT-6 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ALT-7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x16 SDRAM |
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