- 您现在的位置：买卖IC网 > PDF目录384465 > HY57V283220T-6 (HYNIX SEMICONDUCTOR INC) 4 Banks x 1M x 32Bit Synchronous DRAM PDF资料下载
参数资料
| 型号： | HY57V283220T-6 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 4 Banks x 1M x 32Bit Synchronous DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| 封装： | 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件页数： | 2/15页 |
| 文件大小： | 916K |
| 代理商： | HY57V283220T-6 |
HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004
DESCRIPTION
The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the
memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is orga-
nized as 4banks of 1,048,576x32.
HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the
clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally
pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Note)
Hynix supports lead free part for each speed grade with same specification.
Part No.
Clock Frequency
Organization
Interface
Package
HY57V283220(L)T(P)-5
HY5V22(L)F(P)-5
HY57V283220(L)T(P)-55
HY5V22(L)F(P)-55
HY57V283220(L)T(P)-6
HY5V22(L)F(P)-6
HY57V283220(L)T(P)-7
HY5V22(L)F(P)-7
HY57V283220(L)T(P)-H
HY5V22(L)F(P)-H
HY57V283220(L)T(P)-8
HY5V22(L)F(P)-8
HY57V283220(L)T(P)-P
HY5V22(L)F(P)-P
HY57V283220(L)T(P)-S
HY5V22(L)F(P)-S
200MHz
4Banks x 1Mbits x32
LVTTL
86TSOP-II
90Ball FBGA
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
相关PDF资料 |
PDF描述 |
|---|---|
| HY57V283220T-7 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-8 | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-H | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-P | 4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220TP-5 | 4 Banks x 1M x 32Bit Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY57V283220T-7 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-8 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY57V283220T-I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4Mx32|3.3V|4K|55/6/7/8/P/S|SDR SDRAM - 128M |
| HY57V283220T-P | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
发布紧急采购，3分钟左右您将得到回复。