参数资料
型号: HY57V643220CLT-55
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 4 Banks x 512K x 32Bit Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86
封装: 0.400 X 0.875 INCH, 0.5 MM PITCH, TSOP2-86
文件页数: 6/12页
文件大小: 183K
代理商: HY57V643220CLT-55
Rev. 0.8/Aug. 02
6
HY57V643220C
DC CHARACTERISTICS II
(DC operating conditions unless otherwise noted)
Note :
1.I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V643220CT-47/5/55/6/7/8/P/S
4.HY57V643220CLT-47/5/55/6/7/8/P/S
Parameter
Symbol
Test Condition
Speed
Unit
Note
-47
-5
-55
-6
-7
-8
-P
-S
Operating Current
IDD1
Burst Length=1, One bank active
tRAS
tRAS(min), tRP
tRP(min),
IOL=0mA
220
200
190
180
170
150
150
150
mA
1
Precharge Standby
Current
in power down mode
IDD2P
CKE
VIL(max), tCK = 15ns
2
mA
IDD2PS
CKE
VIL(max), tCK =
2
Precharge Standby
Current
in non power down mode
IDD2N
CKE
VIH(min), CS
VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
VDD-0.2V or
0.2V
15
mA
IDD2NS
CKE
VIH(min), tCK =
Input signals are stable.
10
Active Standby Current
in power down mode
IDD3P
CKE
VIL(max), tCK = 15ns
3
mA
IDD3PS
CKE
VIL(max), tCK =
3
Active Standby Current
in non power down mode
IDD3N
CKE
VIH(min), CS
VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
VDD-0.2V or
0.2V
40
mA
IDD3NS
CKE
VIH(min), tCK =
Input signals are
stable
25
Burst Mode Operating
Current
IDD4
tCK
tCK(min),
tRAS
tRAS(min), IOL=0mA
All banks active
CL=3
290
280
260
240
210
180
180
180
mA
1
CL=2
160
160
160
160
160
160
160
Auto Refresh Current
IDD5
tRRC
tRRC(min), 2 banks active
260
250
235
220
210
190
210
190
mA
2
Self Refresh Current
IDD6
CKE
0.2V
2
mA
3
1
4
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