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| 型号： | HY5DV281622AT-5 |
| 英文描述： | SDRAM|DDR|4X2MX16|CMOS|TSSOP|66PIN|PLASTIC |
| 中文描述： | 内存|复员| 4X2MX16 |的CMOS | TSSOP封装| 66PIN |塑料 |
| 文件页数： | 18/27页 |
| 文件大小： | 273K |
| 代理商： | HY5DV281622AT-5 |
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Rev. 0.3/May. 02
18
HY5DV281622AT
BURST DEFINITION
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write com-
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
2
XX0
0, 1
0, 1
XX1
1, 0
1, 0
4
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
8
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
0, 1, 2, 3, 4, 5, 6, 7
7, 6, 5, 4, 3, 2, 1, 0
相关PDF资料 |
PDF描述 |
|---|---|
| HY5DV651622TC-G55 | DDR Synchronous DRAM |
| HY5DV651622TC-G6 | DDR Synchronous DRAM |
| HY5DV651622TC-G7 | DDR Synchronous DRAM |
| HY5DV651622T-G55 | DDR Synchronous DRAM |
| HY5DV651622T-G6 | DDR Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DV281622DT | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-33 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-36 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
| HY5DV281622DT-5 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM |
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